lm5000sdx-6ep National Semiconductor Corporation, lm5000sdx-6ep Datasheet - Page 13

• Manufacturer Part Number: lm5000sdx-6ep
• Description: Enhanced Plastic High Voltage Switch Mode Regulator
• Manufacturer: National Semiconductor Corporation

Operation
where I
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components R
and C
loop. Simply choose values for R
given in the Introduction to Compensation section to set this
pole in the area of 10Hz to 100Hz. The frequency of the pole
created is determined by the equation:
where R
850kΩ. Since R
have much effect on the above equation and can be ne-
glected until a value is chosen to set the zero f
created to cancel out the pole created by the output capaci-
tor, f
currents as shown by the equation, so setting the zero is not
exact. Determine the range of f
and then set the zero f
middle. The frequency of this zero is determined by:
Now R
Check to make sure that the pole f
100Hz range, change each value slightly if needed to ensure
both component values are in the recommended range. After
checking the design at the end of this section, these values
can be changed a little more to optimize performance if
desired. This is best done in the lab on a bench, checking the
load step response with different values until the ringing and
overshoot on the output voltage at the edge of the load steps
is minimal. This should produce a stable, high performance
circuit. For improved transient response, higher values of R
(within the range of values) should be chosen. This will
improve the overall bandwidth which makes the regulator
respond more quickly to transients. If more detail is required,
or the most optimal performance is desired, refer to a more
in depth discussion of compensating current mode DC/DC
switching regulators.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or
just to improve the overall phase margin of the control loop,
another pole may be introduced to cancel the zero created
by the ESR. This is accomplished by adding another capaci-
tor, C
parallel with the series combination of R
should be placed at the same frequency as f
zero. The equation for this pole follows:
P1
C2
C
. The output capacitor pole will shift with different load
C
LOAD
, directly from the compensation pin V
is to set a dominant low frequency pole in the control
O
can be chosen with the selected value for C
is the output impedance of the error amplifier,
is the maximum load current.
C
is generally much less than R
(Continued)
ZC
to a point approximately in the
P1
C
and C
over the expected loads
PC
is still in the 10Hz to
C
C
and C
within the ranges
C
O
to ground, in
Z1
, it does not
C
, the ESR
. The pole
ZC
. f
ZC
C
is
C
C
.
13
To ensure this equation is valid, and that C
without negatively impacting the effects of R
must be greater than 10f
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a
bandwidth of
This is done by calculating the open-loop DC gain, A
this value is known, you can calculate the crossover visually
by placing a −20dB/decade slope at each pole, and a +20dB/
decade slope for each zero. The point at which the gain plot
crosses unity gain, or 0dB, is the crossover frequency. If the
crossover frequency is at less than
phase margin should be high enough for stability. The phase
margin can also be improved some by adding C
cussed earlier in the section. The equation for A
below with additional equations required for the calculation:
where R
mum input voltage, and R
graph "R
teristics section.
SWITCH VOLTAGE LIMITS
In a flyback regulator, the maximum steady-state voltage
appearing at the switch, when it is off, is set by the trans-
former turns ratio, N, the output voltage, V
maximum input voltage, V
where V
and is typically 0.5V for Schottky diodes and 0.8V for ultra-
fast recovery diodes. In certain circuits, there exists a volt-
age spike, V
voltage . Usually, this voltage spike is caused by the trans-
former leakage inductance and/or the output rectifier recov-
ery time. To “clamp” the voltage at the switch from exceeding
its maximum value, a transient suppressor in series with a
diode is inserted across the transformer primary.
If poor circuit layout techniques are used, negative voltage
transients may appear on the Switch pin. Applying a nega-
tive voltage (with respect to the IC’s ground) to any mono-
lithic IC pin causes erratic and unpredictable operation of
that IC. This holds true for the LM5000EP IC as well. When
used in a flyback regulator, the voltage at the Switch pin can
go negative when the switch turns on. The “ringing” voltage
F
L
DSON
is the forward biased voltage of the output diode,
is the minimum load resistance, V
V
SW(OFF)
LL
1
⁄
vs. V
2
, superimposed on top of the steady-state
or less of the frequency of the RHP zero.
mc ) 0.072fs (in A/s)
IN
= V
" in the Typical Performance Charac-
IN
PC
DSON
IN
(Max) + (V
.
(Max):
is the value chosen from the
OUT
1
⁄
2
the RHP zero, the
+V
C2
C
F
IN
)/N
OUT
and C
can be used
is the maxi-
www.national.com
DC
C2
, and the
DC
is given
as dis-
C
. After
, f
PC2