lm5027mhx National Semiconductor Corporation, lm5027mhx Datasheet - Page 3

• Manufacturer Part Number: lm5027mhx
• Description: Voltage Mode Active Clamp Controller
• Manufacturer: National Semiconductor Corporation

Pin
Pin Descriptions
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
OUTSR
TIME3
TIME2
TIME1
COMP
RAMP
AGND
PGND
Name
OUTB
OUTA
REF
VCC
VIN
RT
CS
SS
Description
Input voltage source
Feed-forward modulation ramp
Overlap delay 3
Overlap delay 2
Overlap delay 1
Analog ground
Oscillator frequency control and sync
clock input
Input to the pulse width modulator
Reference Output
Output driver
Output driver
Output driver
Power ground
Start-up regulator output
Current sense input
Soft-start Input
Application Information
Input to the Start-up Regulator. Operating input range is 13V to 90V.
The Absolute Maximum Rating is 105V. For power sources outside of
this range, the LM5027 can be biased directly at VCC by an external
regulator.
An external RC circuit from VIN sets the PWM ramp slope. This pin is
discharged at the conclusion of every cycle by an internal FET. An
internal comparator terminates the PWM pulse if the RAMP pin
exceeds 2.5V thus limiting the maximum volt-second product to the
transformer primary.
An external resistor sets the overlap delay for the active clamp output.
The R
OUTA turn-off (falling edge) to OUTB turn-on (falling edge) pulse delay.
See Fig. 9.
An external resistor sets the overlap delay for the OUTSR output. The
R
turn-off (falling edge) to OUTSR turn-on (rising edge) pulse delay. See
Fig. 9.
An external resistor sets the overlap delay for the active clamp output.
The R
OUTB and OUTSR turn-off to OUTA turn-on pulse delay. See Fig. 9.
Connect directly to Power Ground.
Normally biased at 2V by an internal amplifier. An external resistor
connected between RT and AGND sets the internal oscillator
frequency. The internal oscillator can be synchronized to an external
clock with a frequency higher than the free running frequency set by
the RT resistor.
An external opto-coupler connected to the COMP pin sources current
into an internal NPN current mirror. The PWM duty cycle is at its
maximum value with zero input current, while 1mA reduces the duty
cycle to zero. The current mirror improves the frequency response by
reducing the ac voltage across the opto-coupler detector transistor.
Output of a 5V reference. Maximum output current is 10 mA. Locally
decouple with a 0.1 µF capacitor.
Control output of the active clamp PFET gate. Capable of 1A peak
source and sink current.
Control output of the main PWM NFET gate. Capable of 2A peak
source and sink current.
Control output of the secondary side synchronous rectifier FET gates.
Capable of 3A peak source and sink current.
Connect directly to Analog Ground
Output of the internal high voltage start-up regulator. Regulated at 9.5V
during start-up and 7.5V during run mode. If the auxiliary winding raises
the voltage on this pin above the regulation set point, the internal start-
up regulator will shutdown, thus reducing the IC power dissipation.
Current sense input for cycle-by-cycle current limiting. If the CS pin
exceeds 500mV the output pulse will be terminated, entering cycle-by-
cycle current limit. An internal switch holds CS low for 100 ns after
OUTA switches high to blank leading edge transients.
An internal 22 µA current source charges an external capacitor to set
the soft-start rate.
TIME2
3
TIME3
TIME1
resistor connected between TIME2 and AGND sets the OUTA
resistor connected between TIME3 and AGND sets the
resistor connected between TIME1 and AGND sets the
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