lm5041sdx National Semiconductor Corporation, lm5041sdx Datasheet - Page 12

• Manufacturer Part Number: lm5041sdx
• Description: Cascaded Pwm Controller
• Manufacturer: National Semiconductor Corporation

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Oscillator and Sync Capability
The buck stage will switch at the oscillator frequency and
each push-pull output will switch at half the oscillator fre-
quency in a push-pull configuration. The LM5041 can also
be synchronized to an external clock. The external clock
must have a higher frequency than the free running fre-
quency set by the RT resistor. The clock signal should be
capacitively coupled into the RT pin with a 100pF capacitor.
A peak voltage level greater than 3V is required for detection
of the sync pulse. The sync pulse width should be set in the
15 to 150ns range by the external components. The RT
resistor is always required, whether the oscillator is free
running or externally synchronized. The voltage at the RT pin
is internally regulated to 2V. The RT resistor should be
located very close to the device and connected directly to the
pins of the IC (RT and GND).
Slope Compensation
The PWM comparator compares the current sense signal to
the voltage at the COMP pin. The output stage of the internal
error amplifier generally drives the COMP pin. At duty cycles
greater than 50 percent, current mode control circuits are
subject to sub-harmonic oscillation. By adding an additional
fixed ramp signal (slope compensation) to the current sense
ramp, oscillations can be avoided. The LM5041 integrates
this slope compensation by buffering the internal oscillator
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ramp and summing a current ramp generated by the oscil-
lator internally with the current sense signal. Additional slope
compensation may be provided by increasing the source
impedance of the current sense signal.
Soft-start and Shutdown
The soft-start feature allows the power converter to gradually
reach the initial steady state operating point, thereby reduc-
ing start-up stresses and surges. At power on, a 10uA cur-
rent is sourced out of the soft-start pin (SS) to charge an
external capacitor. The capacitor voltage will ramp up slowly
and will limit the maximum duty cycle of the buck stage. In
the event of a fault as indicated by V
Under-voltage or second level current limit, the output driv-
ers are disabled and the soft-start capacitor is discharged to
ground. When the fault condition is no longer present, a
soft-start sequence will begin again and buck stage duty
cycle will gradually increase as the soft-start capacitor is
charged. The SS pin also serves as an enable input. The
controller will enter a low power state if the SS pin is forced
below the 0.45V threshold.
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the
integrated circuit in the event that the maximum junction
temperature is exceeded. When activated, typically at 165
degrees Celsius, the controller is forced into a low-power
standby state, disabling the output drivers and the bias
regulator. This feature is provided to prevent catastrophic
failures from accidental device overheating.
CC
Under-voltage, line