a6279eet-t Allegro MicroSystems, Inc., a6279eet-t Datasheet

a6279eet-t

Manufacturer Part Number

a6279eet-t

Description

Serial-input Constant-current Latched Led Drivers With Open Led Detection

Manufacturer

Allegro MicroSystems, Inc.

Datasheet

1.A6279EET-T.pdf (18 pages)

Current page: 1 of 18
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Features and Benefits

▪ 3.0 to 5.5 V logic supply range

▪ Schmitt trigger inputs for improved noise immunity

▪ Power-On Reset (POR)

▪ Up to 90 mA constant-current sinking outputs

▪ LED open circuit detection

▪ Low-power CMOS logic and latches

▪ High data input rate

▪ 20 ns typical staggering delay on the outputs

▪ Internal UVLO and thermal shutdown (TSD) circuitry

Packages:

28 pin MLP/QFN (suffix ET)

16 and 24 pin DIP (suffix A)

16 and 24 pin TSSOP (suffix LP)

16 and 24 pin SOIC (suffix LW)

Not to scale

6278-DS, Rev. 4

SUPPLY

OUTPUT

ENABLE

DATA IN

ENABLE

SERIAL

CLOCK

LATCH

LOGIC

REXT

Exposed Pad

(ET and LP packages)

Control Logic

Block

Functional Block Diagram

Regulator

LED Drivers with Open LED Detection

Serial-Input Constant-Current Latched

Output Control Drivers and Open Circuit Detector

OUT0 OUT1

UVLO

Description

The A6278 and A6279 devices are specifically designed for

LED display applications. Each of these BiCMOS devices

includes a CMOS shift register, accompanying data latches,

and NPN constant-current sink drivers. The A6278 contains

8 sink drivers, while there are 16 in the A6279.

The CMOS shift register and latches allow direct interfacing

with microprocessor-based systems. With a 3.3 or 5 V logic

supply, typical serial data-input rates can reach up to 25 MHz.

The LED drive current is determined by the user’s selection of

a single resistor. A CMOS serial data output permits cascading

between multiple devices in applications requiring additional

drive lines. Open LED connections can be detected and signaled

back to the host microprocessor through the SERIAL DATA

OUT pin.

Four package styles are provided: an MLP/QFN surface mount,

0.90 mm overall height nominal (A6279 only); a DIP (type A)

for through-hole applications; and for leaded surface-mount, an

SOIC (type LW) and a TSSOP with exposed thermal pad (type

LP). All package styles for the A6278 are electrically identical

to each other, as are the A6279 package styles. All packages

are lead (Pb) free, with 100% matte tin plated leadframes.

Serial - Parallel Shift Register

Latches

A6278

OUT7 (A6278)

OUT15 (A6279)

and

SERIAL

DATA OUT

GND

LED

A6279

Related parts for a6279eet-t

a6279eet-t Summary of contents

Page 1

Features and Benefits ▪ 3.0 to 5.5 V logic supply range ▪ Schmitt trigger inputs for improved noise immunity ▪ Power-On Reset (POR) ▪ constant-current sinking outputs ▪ LED open circuit detection ▪ Low-power CMOS logic ...

Page 2

... A6279ELP-T 65 pieces per tube A6279ELPTR-T 4000 pieces per 13-in. reel A6279ELW-T 31 pieces per tube A6279ELWTR-T 1000 pieces per 13-in. reel A6279EET-T 73 pieces per tube A6279EETTR-T 1500 pieces per 7-in. reel Parameter LOGIC SUPPLY Voltage Range Load Supply Voltage Range OUTx Current (any single output) ...

Page 3

... LATCH ENABLE 4 OUTPUT ENABLE 21 OUT0 5 20 OUT15 OUT1 6 19 OUT14 OUT2 OUT13 8 OUT3 17 OUT12 9 16 OUT4 OUT11 10 15 OUT5 OUT10 11 OUT6 14 OUT9 12 13 OUT7 OUT8 Function Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 ...

Page 4

... Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Max Unit 5.5 V 2.85 V 2.55 V 86.8 mA 45.9 mA 5.75 mA +6.0 % +6.0 % +6.0 % 5.0 μ 0. 400 mV 0 ...

Page 5

... n-1 n … LATCH ENABLE SERIAL DATA OUT Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com I … n … n-1 n … OUT 5 ...

Page 6

... SU(LE1) H(LE1 W(OE1) SDO n Don't Care high low t H(OE1) t W(OE) t W(OE) t SU(OE P(OE) P(OE D(Total) D(Total) A6278 A6279 SDO n-1 SDO n-2 SDO 0 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 ...

Page 7

... C of the timing diagram on the OE and LE pins ensure W(OE1) voltage on each of the enabled output is lower than V CE Test Condition Error Code Meaning N/A 0 N/A V < Open/TSD CE CE(OCD) V ≥ Normal CE CE(OCD) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com , CE(OCD) 7 ...

Page 8

... Figure 2. Output Current versus Device Voltage Drop T = 25°C A 0.4 0.6 0.8 1 The relationship of EXT are shown in figure 2 for common values 225 Ω R EXT = 470 Ω R EXT = 3900 Ω R EXT 1.2 1.4 1.6 1.8 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2.0 8 ...

Page 9

... However, all of the shift registers will be set with 0, the error bit value. . OUT1 will get set 20 ns after OUT0, (165°C typical), JTSD – T (15°C typical). JTSD JTSDhys Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 ...

Page 10

... × (V × I × 16 D(act greater than and LED , an external voltage reducer (V D(max) LED Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com , × must be DROP 10 ...

Page 11

... LW Package 50° 100 0 DC (%) A Package 85° 100 0 DC (%) LP Package 85° 100 0 DC (%) LW Package 85° 100 0 DC (%) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 100 100 100 11 ...

Page 12

Page 13

... ET package, 24-pin, measured on 4-layer board based on JEDEC standard 5.0 4.0 3.0 2.0 1.0 0 125 150 25 (°C) A Value A6279 50 75 100 125 Ambient Temperature, T (°C) A Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W 150 13 ...

Page 14

... Metric dimensions (mm) in brackets, for reference only 2.92 (reference JEDEC MS-001 AF) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 14 ...

Page 15

... PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com ...

Page 16

Page 17

... JEDEC MS-013 AD) 0.30 .012 Dimensions exclusive of mold flash, gate burrs, and dambar protrusions 0.10 .004 Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 17 ...

Page 18

... The in for ma tion in clud ed herein is believed rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. ...

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