sc4524a Semtech Corporation, sc4524a Datasheet - Page 13
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sc4524a
Manufacturer Part Number
sc4524a
Description
Sc4524a 28v 2a Step-down Switching Regulator
Manufacturer
Semtech Corporation
Datasheet
1.SC4524A.pdf
(18 pages)
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12
12
10
10
ω
ω
PWM
PWM
V
V
S
S
p
p
V
V
45
45
⋅
⋅
−
−
,
,
FB
FB
10
10
)
)
n
n
O
O
3
3
2
2
,
,
G
G
28
28
1 (
1 (
80
80
pF
pF
)
)
3
3
1
1
nF
nF
1 (
1 (
=
=
CA
CA
1
1
3
3
1
1
⋅
⋅
+
+
Applications Information (Cont.)
The block diagram in Figure 7 shows the control loops of a
buck converter with the SC4524A. The inner loop (current
loop) consists of a current sensing resistor (R
and a current amplifier (CA) with gain (G
loop (voltage loop) consists of an error amplifier (EA), a
PWM modulator, and a LC filter.
Since the current loop is internally closed, the remaining
task for the loop compensation is to design the voltage
compensator (C
For a converter with switching frequency F
inductance L
control (V
given by:
This transfer function has a finite DC gain
an ESR zero F
a dominant low-frequency pole F
and double poles at half the switching frequency.
⋅
⋅
22
22
22
22
⋅
⋅
R
R
⋅
⋅
+
+
10
10
6
6
s
s
22
22
S
S
1 .
1 .
s
s
/
/
.
.
1 .
1 .
1
1
FB
FB
1
1
k 3
k 3
R
R
⋅
⋅
3
3
ω
ω
1 .
1 .
2
2
⋅
⋅
ESR
ESR
⋅
⋅
R
R
R
R
ω
ω
n
n
R
R
⋅
⋅
C
C
C
C
10
10
C
C
C
C
G
G
G
G
R
R
C
C
C
C
C
C
C
C
A
A
A
A
A
A
A
A
ω
ω
V
V
V
V
V
V
V
V
10
10
π
π
REF
REF
22
22
Q
Q
⋅
⋅
7
7
7
7
7
7
o
o
o
o
c
c
c
c
PWM
PWM
PWM
PWM
7
7
Figure 7. Block diagram of control loops
C
C
C
C
C
C
C
C
5
5
5
5
8
8
8
8
Z
Z
5
5
5
5
8
8
8
8
F
F
p
p
10
10
C
C
1
1
+
+
C
C
−
−
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
≈
≈
=
=
=
=
3
3
=
=
C
O
O
+
+
3
3
-
-
⋅
⋅
C
C
CONTROLLER AND SCHOTTKY DIODE
CONTROLLER AND SCHOTTKY DIODE
) to output (V
s
s
)
)
10
10
3
3
10
10
. 0
. 0
1 (
1 (
10
10
R
R
. 0
. 0
1 (
1 (
R
R
−
−
−
−
−
−
−
−
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
=
=
≈
≈
≈
≈
O
O
⋅
⋅
2
2
g
g
EA
EA
g
g
1
1
R
R
⋅ π
⋅ π
ESR
ESR
C
C
⋅ π
⋅ π
2
2
=
=
Z
π
π
20
20
20
20
28
28
⋅ π
⋅ π
⋅ π
⋅ π
π
π
π
π
π
π
20
20
20
20
28
28
. 0
. 0
/
/
C5
C5
R7
R7
⋅
⋅
, output capacitance C
G
G
G
G
+
+
+
+
m
m
m
m
10
10
10
10
−
−
1
1
4
4
at
A
A
A
A
F
F
O
O
⋅ π
⋅ π
20
20
20
20
F
F
F
F
F
F
12
12
ω
ω
V
V
6
6
C
C
C
C
CA
CA
V
V
CA
CA
1
1
1
1
1
1
16
16
16
16
600
600
45
45
1
1
600
600
s
s
s
s
C
C
Z
Z
P
P
5
Z
Z
P
P
,
,
=
=
FB
FB
, R
1
1
⋅
⋅
⋅
⋅
O
O
2
2
n
n
1
1
1
1
1
1
COMP
COMP
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
R
R
R
R
⋅
⋅
15
15
O
O
15
15
80
80
/
/
/
/
log
log
log
log
log
log
log
log
10
10
10
10
pF
pF
20
20
20
20
⋅
⋅
⋅
⋅
R
R
)
)
R
R
1
1
R
R
R
R
R
R
3
3
nF
nF
G
G
G
G
Vramp
Vramp
9 .
9 .
9 .
9 .
R
R
R
R
ω
ω
ω
ω
Vc
Vc
7
⋅
⋅
⋅
⋅
,
,
6
6
0 .
0 .
3 .
3 .
, and C
10
10
7
7
7
7
7
7
7
7
10
10
PWM
PWM
PWM
PWM
S
S
p
p
S
S
⋅
⋅
⋅
⋅
p
p
−
−
⋅
⋅
−
−
10
10
10
10
)
)
10
10
)
)
3
3
3
3
,
,
,
,
1
1
G
G
28
28
G
G
28
28
1 (
1 (
1 (
1 (
C8
C8
CA
CA
3
3
3
3
1
1
MODULATOR
MODULATOR
1
1
V
V
0 .
0 .
1 (
1 (
=
=
=
=
=
=
1 (
1 (
CA
CA
CA
CA
1
1
1
1
1
1
3
3
O
O
3
3
1
1
1
1
⋅
⋅
⋅
⋅
3
3
O
+
+
+
+
PWM
PWM
15
15
V
V
⋅
⋅
⋅
⋅
22
22
22
22
22
22
22
22
R
R
) transfer function in Figure 7 is
R
R
⋅
⋅
⋅
⋅
+
+
+
+
⋅
⋅
ω
ω
6
6
6
6
s
s
8
s
s
22
22
22
22
S
S
).
22
22
S
S
−
−
1 .
1 .
1 .
1 .
s
s
s
s
Z
Z
/
/
/
/
9 .
9 .
Rs
Rs
.
.
1 .
1 .
1
1
1
1
.
.
1 .
1 .
k 3
k 3
k 3
k 3
R
R
R
R
1
1
⋅
⋅
⋅
⋅
ω
ω
ω
ω
=
=
1 .
1 .
1 .
1 .
2
2
⋅
⋅
dB
dB
2
2
⋅
⋅
ESR
ESR
⋅
⋅
ESR
ESR
⋅
⋅
⋅
⋅
n
n
n
n
10
10
10
10
10
10
ω
ω
ω
ω
R
R
10
10
π
π
π
π
10
10
Io
Io
Q
Q
Q
Q
⋅
⋅
⋅
⋅
F
F
p
p
p
p
F
F
10
10
10
10
ESR
ESR
C
C
C
C
P
1
1
1
1
+
+
+
+
C
C
C
C
−
−
−
−
−
−
1
1
≈
≈
≈
≈
3
3
3
3
at
O
O
O
O
3
3
3
3
C
C
C
C
6
6
s
s
C
C
SW
SW
s
s
)
)
3
3
3
3
)
)
R
R
R
R
=
=
=
=
O
O
O
O
O
⋅
⋅
⋅
⋅
2
2
⋅
⋅
2
2
O
O
1
1
1
1
C
C
C
C
2
2
=
=
2
2
1
1
=
=
3
3
. 0
. 0
. 0
. 0
and loading R, the
/
/
/
/
⋅
⋅
⋅
⋅
,
,
O
O
⋅ π
⋅ π
O
O
⋅ π
⋅ π
0 .
0 .
3 .
3 .
12
12
12
12
ω
ω
ω
ω
V
V
V
V
V
V
CA
V
V
45
45
45
45
,
,
,
,
FB
FB
FB
FB
O
O
2
2
2
2
n
n
n
n
O
O
L1
L1
=28). The outer
80
80
80
80
pF
pF
pF
pF
)
)
)
)
nF
nF
nF
nF
Co
Co
Resr
Resr
=
=
15
15
⋅
⋅
⋅
⋅
10
10
10
10
SW
(8)
s
9 .
9 .
=6.mW)
, output
1
1
1
1
3
3
3
3
dB
dB
⋅
⋅
⋅
⋅
ω
ω
ω
ω
Vo
Vo
22
22
22
22
R4
R4
R6
R6
Z
Z
Z
Z
=
=
=
=
⋅
⋅
⋅
⋅
10
10
10
10
R
R
R
R
ESR
ESR
ESR
ESR
−
−
1
1
1
1
−
−
6
6
6
6
C
C
C
C
Including the voltage divider (R
feedback transfer function is found and plotted in Figure
8 as the converter gain.
Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
is sufficient for voltage loop compensation. As shown in
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at F
at F
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
Therefore, the procedure of the voltage loop design for
the SC4524A can be summarized as:
() Plot the converter gain, i.e. control to feedback transfer
function.
(2) Select the open loop crossover frequency, F
0% and 20% of the switching frequency. At F
required compensator gain, A
ceramic output capacitors, the ESR zero is neglected and
the required compensator gain at F
⋅
⋅
⋅
⋅
O
O
O
O
1
1
1
1
3
3
3
3
,
,
,
,
0 .
0 .
0 .
0 .
3 .
3 .
3 .
3 .
P
. The integrator is used to boost the gain at low
A
A
A
A
=
=
=
=
Figure 8. Bode plots for voltage loop design
C
C
C
C
15
15
15
15
=
=
=
=
9 .
9 .
−
−
−
−
9 .
9 .
20
20
20
20
dB
dB
dB
dB
⋅
⋅
⋅
⋅
log
log
log
log
G
G
28
28
CA
CA
1
1
⋅
⋅
R
R
6
6
S
S
Z
1 .
1 .
1
1
, and a high frequency pole
⋅
⋅
C
. In typical applications with
2
2
⋅
⋅
10
10
π
π
4
F
F
1
1
C
C
−
−
and R
3
3
C
C
C
can be estimated by
O
O
⋅
⋅
2
2
⋅
⋅
⋅ π
⋅ π
V
V
6
V
V
), the control to
FB
FB
SC4524A
O
O
80
80
⋅
⋅
C
10
10
, between
C
, find the
(9)
1
1
3
3
⋅
⋅
22
22
3
⋅
⋅
10
10
−
−
6
6
⋅
⋅
1
1
. 3
. 3
0 .
0 .