lm27212 National Semiconductor Corporation, lm27212 Datasheet - Page 17

• Manufacturer Part Number: lm27212
• Description: Two-phase Current-mode Hysteretic Buck Controller
• Manufacturer: National Semiconductor Corporation

Design Considerations
SETTING CURRENT LIMIT
The current limit comparator compares the voltage pre-
established across the current limit set resistor (R13 in Fig-
ure 1) and the voltage across the current sense resistors.
The current sourced by the ILIMREF pin is 3 times ih. The
equation to determine R13 is:
where I
RS1 is the sense resistance and I
the ILIMREF pin.
Example: RS1 = RS2 = 3mΩ, I
So R13 = 210Ω. Note I
current plus inductor current ripple plus some margin. Sup-
pose the maximum output current is 24A, and inductor ripple
current is
margin of 8A in load current.
SETTING THE LOAD LINE SLOPE
Refer to Figure 1. In two-phase operation mode, the load line
is set by the ratio between RR1 and RR2. The equation is:
Example: RS1 = 3mΩ, r = -3mΩ.
So RR2 divided by RR1+RR2 is 0.5
It is suggested that the user choose the parallel combination
of RR1 and RR2 to be close to RH1 or RH2 to cancel the DC
offset caused by bias current of the CMPx pins. So if RH1 is
60Ω, then RR1 = RR2 = 120Ω.
peak
±
5A. So choosing an I
is the maximum allowed peak inductor current,
peak
is usually half of maximum output
peak
peak
ref
is the current sourced by
= 21A, I
value of 21A gives us a
(Continued)
ref
= 300µA.
17
Special PCB Layout
Considerations
1. Grounding
There are two grounds, one is power ground, the other is
signal ground. Power ground is the plane which DGND,
power FETs, input and output capacitors are directly con-
nected to. Signal ground is a separate plane that R6 / R8 /
C3 / C7 and SGND / TGND (if LLP, also the thermal pad) are
connected to. Signal ground should connect to the ground
sense via through a trace.
PGND should connect to the source pins of Channel 1
bottom FETs through a separate trace. If vias have to be
used during routing, make sure the vias are isolated from all
ground planes, polygons and fills.
2. Sensing
The VCORE sense via should be as close to output bulk
capacitors as possible and should be symmetrical with re-
spect to the two phases. It should also be isolated from any
VCORE planes / polygons / fills other than those on the top
layer. The VCORE sense signal should be used for the
SENSE pin, R13 and R14. This trace should be kept away
from power inductors.
The ground sense via is the only place power ground con-
nects to signal ground. The via should be as close to the
output bulk capacitors as possible. It should be symmetrical
with respect to the two phases. It should also be isolated
from any ground planes/polygons/fills other than those on
top layer. The control IC should be close to this Via.
SW1 sense needs a trace from the SW1 pin to the drain pins
of the Channel 1 bottom FETs. If vias have to be used during
routing, make sure the vias are isolated from all SW1 planes
/ polygons / fills. Keep the SW1 sense trace as close as
possible to the SRCK1 trace.
Current sense vias should connect to the current sense
resistor pads through a top layer trace. The vias should be
isolated from all planes / polygons / fills on the same net but
not on the top layer. They should connect to R11 / R12 and
R18 / R19 through an isolated trace. Current sense traces
should be kept away from power inductors.
www.national.com