ncp3120 ON Semiconductor, ncp3120 Datasheet - Page 12

• Manufacturer Part Number: ncp3120
• Description: Dual 2.0 A, Step-down Dc/dc Switching Regulator
• Manufacturer: ON Semiconductor

Introduction
voltage mode buck regulator. Each channel is identical and
has a 2.0 A internal P-FET, compensation, feedback,
programmable soft-start, enable and Powergood pins.
These circuits also share the same input voltage, reference
voltage, thermal shutdown, undervoltage detect and master
oscillator. A simple auto-tracking and sequencing
capability can be implemented using the SEQ/TRACK/SS
pins.
from a common oscillator, ensures a 180° phase differential
between channels. This 180° phase shift between the two
channels reduces the common input capacitor requirement
and improves the noise immunity. The NCP3120 switching
frequency is set by an external resistor and is adjustable
between 200-750 kHz. This allows application optimization
between efficiency and total solution size.
voltage divider to the FB input pin and compared with the
reference voltage, then the voltage difference is amplified
through the internal transconductance error amplifier. The
output current of the transconductance error amplifier
(OTA) is presented at the COMP node where an RC network
compensates the regulation control system loop.
function, which is implemented through the error amplifier
and the external compensation capacitor. This feature
prevents stress to the power components and limits output
voltage overshoot during start-up.
Undervoltage Lockout (UVLO)
unexpected behavior does not occur when V
support the internal rails and power the converter. In case the
input voltage is higher than the UVLO threshold (4.3 V
standard value, rising voltage), the step down converter
operation can be started. This circuit has a 0.25 V hysteresis
(typical). If the falling trip is activated, switching ceases and
eventually the circuit turns off. When the input circuit is in
this state, the currrent consumption is equal 5 mA (typical).
Fixed Frequency Operation
generating a PWM signal. During normal operation, the
oscillator generates an accurate pulse at the beginning of
each switching cycle to turn on the main switch. The main
switch will be turned off when the ramp signal intersects
with the output of the error amplifier (COMP pin voltage).
Therefore, the switch duty cycle can be modified to regulate
the output voltage to the desired value as line and load
conditions change.
the component selections, especially the magnetic
component design, become very easy. The oscillator
The NCP3120 is a dual channel non-synchronous PWM
The fixed-frequency programmable architecture, driven
The output voltage is fed back through an external resistor
The NCP3120 features a programmable soft-start
Undervoltage lockout (UVLO) is provided to ensure that
The NCP3120 uses a constant frequency architecture for
The major advantage of fixed frequency operation is that
in
is too low to
DETAILED DESCRIPTION
http://onsemi.com
NCP3120
12
frequency of the NCP3120 is programmable from 200 kHz
to 750 kHz using an external resistor connected from the RT
pin to ground. The oscillator works on the double frequency
internally. Therefore, both channels have a 180° phase shift
of the SW pins.
Out-of-Phase Operation
channel is delayed by half the switching cycle. This delay is
supervised by the oscillator, which supplies a clock signal to
the second channel which is 180° out of phase with the clock
signal of the first channel. The advantages of out-of-phase
synchronization are many. Since the input current pulses are
interleaved with one another, the overlap time is reduced.
The effect of this overlap reduction is to attenuate the input
filter requirement, allowing the use of smaller components.
Additionally, since peak current occurs during a shorter time
period, emitted EMI is also reduced, thereby reducing
shielding requirements.
Enable Input
Logic low on SEQ forces the NCP3120 into shutdown
mode. Connect SEQ to EN for normal operation of a
standalone device. In shutdown mode, the NCP3120 is
turned off and the supply current is reduced to less than
100 mA. In case the enable function will not be required, EN
and SEQ pin have to be pulled high or connected directly to
V
voltage may be pulled high on the output pins. The output
capacitors should be discharged. If this condition is not
observed when NCP3120 is enabled, the regulator does not
start switching. This helps to prevent improper operation of
the NCP3120 circuit due to the implemented tracking and
sequencing features.
Soft-Start/Stop Control
external power supply by controlling the inrush current
peaks to charge the output capacitor and DC load and to
attain smoothly increasing output voltage at start-up. A soft
start circuit forces the error amplifier output to follow a
prescribed voltage ramp when turning on and off. The output
capacitor is discharged when V
thermal shutdown or overload detection occurs. The circuit
input is presented as a voltage ramp generated by internal
current sources tied to an external SS capacitor. The external
capacitor on the soft-start node is charged/discharged by the
8.75 mA current from the constant current source, and the
voltage on the SS node controls the OTA amplifier output
voltage until the SS capacitor is charged/discharged to a
voltage higher than 0.8 V.
in
In out-of-phase operation, the turn-on of the second
Pull the EN enable input high to enable the operation.
Note: For proper operation of the NCP3120 circuit, no
This capacitor limits the maximum demand on the
(max 8 V).
in
goes under the UVLO as