ncl30051 ON Semiconductor, ncl30051 Datasheet - Page 9

• Manufacturer Part Number: ncl30051
• Description: Ncl30051 Product Preview Two Stage Pfc And Resonant Half Bridge Controller Combo For Led Lighting
• Manufacturer: ON Semiconductor

Half−Bridge Disable
high side drivers are disabled once the voltage on the OSC
pin is brought below the half−bridge disable threshold,
V
pulling down on the oscillator pin using a transistor or open
collector/drain device. Once the oscillator pin is released
the oscillator capacitor returns to its normal operating
range and the half bridge is re−enabled. The low side
half−bridge driver generates the first drive pulse during
initial power up or re−starting of the half−bridge. This
ensures boost voltage is generated to supply the high side
driver.
Voltage Reference
the controller to ease compensation requirements. The
reference voltage is typically 7.0 V. A 0.1 mF is required for
stability. The reference should not be loaded with external
circuitry.
PFC Regulator
(CrM). In CrM, the PFC inductor current, I
at the end of the switch cycle as shown in Figure 4. As seen
in Figure 4, the average input current, I
the ac line voltage, V
constant on time (t
(V
relationship between on time and system operating
conditions.
where, P
inductance and h is the system efficiency.
HB(DIS)
The half−bridge oscillator and the half−bridge low and
The internal voltage reference, V
The PFC stage operates in critical conduction mode
High power factor is achieved in CrM by maintaining a
ac(RMS)
out
(typically 1.955 V). This can be accomplished by
) and load conditions. Equation 2 shows the
Figure 4. Inductor Current in CrM
is the output power, L is the PFC inductor
t
on
on
in(t)
) for a given RMS input voltage
+
.
h @ V
2 @ P
ac(RMS)
out
@ L
REF
2
in(t)
, is brought out of
L(t)
, is in phase with
, reaches zero
http://onsemi.com
(eq. 2)
9
On Time Control
external timing capacitor on the PCT pin, C
constant current source, I
compared to the control voltage, V
voltage is constant for a given RMS line voltage and output
load, satisfying Equation 2. A voltage offset, V
is added to the C
range. The block diagram of the constant on time section
is shown in Figure 5.
2.25 V and 5.65 V. An offset voltage greater than the
minimum PControl clamp voltage is added to the C
prior to comparing it to the control voltage signal. This
allows the PFC stage to stop the drive pulses (0% duty ratio)
and regulate at light loads. The delta between the Pcontrol
voltage needed to generate a PDRV pulse and the minimum
PControl Clamp voltage is V
C
drive pulse terminates once the C
voltage threshold, V
inductor current reaches zero detected by a transition on the
ZCD pin or the maximum off has been reached.
voltage is reached at low line and full load. In this operating
PControl
T
The NCL30051 controls the on time by charging an
Figure 5. Constant On Time Control Block Diagram
The PControl voltage is internally clamped between
The timing capacitor is discharged and held low once the
The timing capacitor is sized such that the C
PZCD
ramp voltage plus offset reaches V
PCS
PFB
PCT
V
DD
I
PFB
LEB
I
PCT(C)
T
> 5.65 V
< 2.25 V
ramp to account for the control voltage
Clamp
Clamp
V
PCT(peak)
+
−
DD
V
PUVP
+
−
PFC UVP
Comparator
V
Shifter
−
+
Amplifier
−
+
V
+
−
PCS(ILIM)
Level
PCT(C)
PREF
PCT(offset)
. A new cycle starts once the
Error
PFC
−
+
Comparator
PCS
T
V
. The C
CC
V
voltage reaches its peak
+
POVP
−
+
Good
PControl
Comparator
Comparator
.
+
−
On time
V
PFC OVP
+
−
PControl
Comparator
ZCD
T
ZCD
+
−
. The control
PFCoff
ramp is then
T
S
R
Dominant
Reset
Latch
. The PFC
ramp peak
PCT(offset)
T
, with a
T
ramp
Q
Q
,