a4930 Allegro MicroSystems, Inc., a4930 Datasheet - Page 5

• Manufacturer Part Number: a4930
• Description: A4930 Single Phase Fan Pre-driver
• Manufacturer: Allegro MicroSystems, Inc.

A4930
VREG5
to ground. VREG5 can supply up to 15 mA, which can used to
power the external Hall element.
VREG8
ground. VREG8 is used to power the low-side gate drive circuits.
Charge Pump
above V
is internally monitored, and in the case of a fault condition, the
outputs of the device are disabled.
Lock Detect
to ensure that the FG output signal is continuously changing. The
length of time allowed for a stoppage before evaluating a locked
condition, t
duces a triangle waveform with a frequency that is linearly related
to the capacitor value. The definition of t
of this triangle waveform, and its value can be calculated as:
If an FG transition is not detected within t
the appropriate source driver and hold both sink drivers on. The
circuit will automatically retry with a 15:1 ratio of off-time to on-
time. An RD pin logic high indicates this fault condition.
Current Limit and Soft Start
power supply, peak current is controlled. Initially, with the fan
at a stand-still, the turn-on of the bridge results in current rising
according to the L/R time constant of the motor. To prevent over-
stress, this peak current is regulated by an internal PWM control
circuit. When the outputs of the full-bridge are turned on, current
increases in the motor winding until it reaches a value given by:
The R
within the range of 200 to 500 mV, according to the relationship:
At the trip point, the sense comparator resets the source enable
latch, turning off the source driver. At this point, load inductance
causes the current to recirculate for 50 μs.
SENSE
This pin should be decoupled with a 0.1 μF capacitor
This pin should be decoupled with a 0.1 μF capacitor to
BB
LD
to drive the high-side MOSFETs. The VCP voltage
value should be chosen to keep the peak sense voltage
The IC detects a locked rotor condition by checking
, is set by capacitor connected to CLD pin. C
The charge pump is used to generate a supply
I
R
TRIP
t
LD
SENSE
= C
= V
< 500 mV / I
LD
REF
× (10 s / μF) .
/ 5 × R
To minimize demand on the
SENSE
TRIP .
LD
LD
is defined as 8 cycles
.
, the IC will disable
Functional Description
LD
(1)
(2)
(3)
pro-
A soft start capacitor, CSS, can be connected to the SS pin to set
the rate for slowly ramping-up the load current to the maximum
value, according to the relationship:
In this case the current limit will likely not be achieved and there
will be less demand on the input power supply. If this feature is
not utilized, the SS pin should be left open.
Synchronous Rectification
load current recirculates. The A4930 synchronous rectification
feature turns on the appropriate MOSFETs during current decay,
and effectively shorts out the body diodes of the low R
driver.
TSD
outputs will be disabled until the internal temperature falls below
a hysteresis level of 15°C.
Shutdown
temperature, or low voltage on VCP or VBB, the outputs of
the device are disabled until the fault condition is removed. At
power-up the UVLO circuit disables the drivers until the UVLO
threshold is reached.
CPWM
circuit. The value is typically from 15 to 30 kHz.
PWM
the range from 0 to 6 V. The duty cycle, DC, of the input to this
pin is converted to an analog voltage that is output on the SIN
terminal as follows:
If the PWM input is not used, then leave this pin open circuit.
Direct external PWM control can be utilized by applying the
signal to the SIN input (refer to the Applications Information sec-
tion). This can be implemented to create different PWM input to
PWM output transfer functions.
If the die temperature exceeds approximately 165°C, the
The IC accepts a direct input PWM signal with a level in
Single Phase Fan Pre-Driver
This capacitor sets the frequency of the internal PWM
In the event of a fault due to excessive junction
t
SS
V
= (C
SIN
= 3.5 V –2 × DC .
SS
× V
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
When a PWM off-cycle is triggered,
REF
) / 3.3E–6
.
DS(on)
(4)
(5)
5