a6812ea Allegro MicroSystems, Inc., a6812ea Datasheet - Page 7

• Manufacturer Part Number: a6812ea
• Description: Dabic-iv 20-bit Serial-input Latched Source Driver
• Manufacturer: Allegro MicroSystems, Inc.

A6812
A. Data Active Time Before Clock Pulse
B. Data Active Time After Clock Pulse
C. Clock Pulse Width, t
D. Time Between Clock Ac ti va tion and Strobe, t
E. Strobe Pulse Width, t
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable with increased supply voltage; op-
er a tion at high temperatures will reduce the specifi ed max i mum
clock frequency.
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On suc ceed ing CLOCK pulses, the registers shift
Serial Data present at the input is trans ferred to the shift
(Data Set-Up Time), t
(Data Hold Time), t
w(CH)
w(STH)
h(D)
su(D)
.............................................. 50 ns
............................................. 25 ns
........................................... 50 ns
BLANKING
DATA OUT
BLANKING
........................................ 25 ns
STROBE
DATA IN
SERIAL
SERIAL
CLOCK
TIMING REQUIREMENTS and SPECIFICATIONS
OUT
OUT
N
N
A
DATA
(Logic Levels are V
su(C)
50%
B
...... 100 ns
C
50%
LOW = ALL OUTPUTS ENABLED
D
50%
50%
t
p(CH-SQX)
t
en(BQ)
50%
HIGH = ALL OUTPUTS BLANKED (DISABLED)
DD
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
spective latch when the STROBE is high (serial-to-par al lel con-
ver sion). The latches will continue to accept new data as long
as the STROBE is held high. Ap pli ca tions where the latches are
bypassed (STROBE tied high) will require that the BLANKING
input be high during serial data entry.
ers are disabled (OFF); the pnp active pull-down sink drivers are
ON. The in for ma tion stored in the latches is not affected by the
BLANKING input. With the BLANK ING input low, the outputs
are con trolled by the state of their re spec tive latches.
E
t
p(STH-QL)
and Ground)
t
10%
p(STH-QH)
Information present at any register is transferred to the re-
When the BLANKING input is high, the output source driv-
DABiC-IV 20-Bit Serial-Input
t
dis(BQ)
DATA
90%
t
DATA
r
10%
Latched Source Driver
90%
50%
Dwg. WP-030A
Dwg. WP-029
t
DATA
f
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
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