a6b273klwtr-t Allegro MicroSystems, Inc., a6b273klwtr-t Datasheet

a6b273klwtr-t

Manufacturer Part Number

a6b273klwtr-t

Description

8-bit Latched Dmos Power Driver

Manufacturer

Allegro MicroSystems, Inc.

Datasheet

1.A6B273KLWTR-T.pdf (10 pages)

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Caution: These CMOS devices have input static

protection (Class 3) but are still susceptible to damage if

exposed to extremely high static electrical charges.

Note that the A6B273KA (DIP) and the A6B273KLW

(SOIC) are electrically identical and share a common

terminal number assignment.

Output Voltage, V

Output Drain Current,

Single-Pulse Avalanche Energy,

Logic Supply Voltage, V

Input Voltage Range,

Package Power Dissipation,

Operating Temperature Range,

Storage Temperature Range,

* Each output, all outputs on.

† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.

ABSOLUTE MAXIMUM RATINGS

GROUND

CLEAR

OUT

Continuous, I

Peak, I

OUT

................................... -0.3 V to +7.0 V

........................................... See Graph

................................. -40

................................. -55

................................................. 30 mJ

................................... 500 mA†

at T

.......................... 150 mA*

............................... 50 V

= 25

.................. 7.0 V

C to +125

C to +150

Dwg. PP-015-2A

STROBE

LOGIC

SUPPLY

OUT

Selection Guide

*Pb-based variants are being phased out of the product line. Some variants cited in

this footnote are in production but have been determined to be LAST TIME BUY or

NOT FOR NEW DESIGN. This classification indicates that sale of this device is currently

longer available. Status change for LAST TIME BUY: October 31, 2006. Deadline for

receipt of LAST TIME BUY orders: April 27, 2007. These variants include: A6B273KLW and

A6B273KLWTR. Status change for NOT FOR NEW DESIGN: May 1, 2006. These variants

include: A6B273KA.

restricted to existing customer applications. The variants should not be purchased for new

design applications because obsolescence in the near future is probable. Samples are no

A6B273KLW-T

A6B273KLWTR-T

6B273

triggered D-type) data latches and DMOS outputs for systems requiring

relatively high load power. Driver applications include relays, sole-

noids, and other medium-current or high-voltage peripheral power

loads. The CMOS inputs and latches allow direct interfacing with

microprocessor-based systems. Use with TTL may require appropriate

pull-up resistors to ensure an input logic high.

drivers are disabled (the DMOS sink drivers turned OFF) with the

CLEAR input low. The A6B273KA/KLW DMOS open-drain outputs

are capable of sinking up to 500 mA. Similar devices with reduced

package. The A6B273KLW is furnished in a 20-lead wide-body,

small-outline plastic package (SOIC) with gull-wing leads for surface-

mount applications. Copper lead frames, reduced supply current

requirements, and low on-state resistance allow both devices to sink

150 mA from all outputs continuously, to ambient temperatures over

85°C.

FEATURES

■ 50 V Minimum Output Clamp Voltage

■ 150 mA Output Current (all outputs simultaneously)

■ 5 Ω Typical

■ Low Power Consumption

■ Replacements for TPIC6B273N and TPIC6B273DW

Part Number

DS(on)

The A6B273KA and A6B273KLW combine eight (positive-edge-

The DMOS output inverts the DATA input. All of the output

The A6B273KA is furnished in a 20-pin dual in-line plastic

are available as the A6273KA/KLW.

Pb-free*

DS(on)

Yes

DMOS POWER DRIVER

20-pin SOICW

Package

8-BIT LATCHED

1000 per reel

37 per tube

Packing

(°C/W)

θJA

(°C/W)

θJC

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a6b273klwtr-t Summary of contents

Page 1

... Replacements for TPIC6B273N and TPIC6B273DW Selection Guide Part Number Pb-free* A6B273KLW-T Yes A6B273KLWTR-T Yes ° C *Pb-based variants are being phased out of the product line. Some variants cited in this footnote are in production but have been determined to be LAST TIME BUY or ° ...

Page 2

... LATCHED DMOS POWER DRIVER 2.5 2.0 1.5 1.0 0 100 AMBIENT TEMPERATURE Dwg. EP-010-16 125 150 Dwg. GS-004B 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 W Copyright © 2002 Allegro MicroSystems, Inc. OUT Dwg. EP-063 H R ...

Page 3

IN 1 STROBE IN 2 LOGIC SUPPLY CLEAR (ACTIVE LOW) www.allegromicro.com D C1 CLR CLR D C1 CLR D C1 CLR D C1 CLR ...

Page 4

LATCHED DMOS POWER DRIVER Typical Data and is for design information only. DD NOTE — Pulse test, duration 100 s, duty cycle 2%. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) ...

Page 5

INx STROBE OUTPUTx Input Active Time Before Strobe (Data Set-Up Time), t Input Active Time After Strobe (Data Hold Time), t Input Pulse Width, t Input Logic High, V Input Logic Low, V INPUT 500 mA ...

Page 6

LATCHED DMOS POWER DRIVER Terminal No. Terminal Name 1 CLEAR OUT 1 5 OUT 2 6 OUT 3 7 OUT GROUND 11 STROBE ...

Page 7

MAX 0.015 MIN 20 7.11 6.10 1 5.33 MAX 0.39 MIN 0.558 0.356 NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness ...

Page 8

LATCHED DMOS POWER DRIVER 20 0.2992 0.2914 0.020 1 0.013 0.0926 0.1043 0.0040 20 7.60 7.40 0.51 1 0.33 2.65 2.35 0.10 NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing ...

Page 9

... DMOS POWER DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current ...

Page 10

LATCHED DMOS POWER DRIVER * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part number includes additional ...

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