ml4828cs Microsemi Corporation, ml4828cs Datasheet - Page 7

• Manufacturer Part Number: ml4828cs
• Description: Bicmos Phase Modulation/soft Switching Controller
• Manufacturer: Microsemi Corporation

SOFT START TIME CONSTANT
During start up, the output voltage is much lower than the
steady state value. Without soft start circuitry, the error
amplifier output (EAO) would swing all the way to the
upper limit and the phase modulator would issue pulses
with full duty cycle, possibly causing output overshoot. To
ensure smooth start up, EAO (pin 8) is pulled low and
then gradually released through the charging of an
external soft start capacitor connected to SS (pin 7). The
soft start charging current is internally set at 25 A. Hence,
EAO will rise with a time constant of:
For example, with C
will be:
FAULT TIME CONSTANT AND RESTART DELAY
Figure 5 shows the internal circuitry and external
components involved in fault detection. During normal
operation, RST (pin 12) is discharged to ground through
the external resistor R
threshold of 1V. R
across it will be equal to the I
maximum desired I
across R
terminating the present power cycle, and at the same time
activating the fault logic to turn on the 500 A current
SENSE
exceeds 1V, the I
SENSE
SWITCH
SS
dv
dt
RST
= 25 F, the soft start rate of change
I
R
is selected so that the voltage
SWITCH
R
dv
dt
RST
. The I
SENSE
Figure 5. Over-Current, Soft-Start, and Integrating Fault Detect Circuits.
25
25
current. When the voltage
R1
25
LIM
C
A
F
LIM
LIM
SS
A
threshold at the
C
comparator has a
SS
C
1
comparator trips,
RST
V
s
C1
20
12
7
RST
SS
I
LIM
I
RST
V+
(10)
(9)
1V
source I
For proper design, R
of 100k ). This will cause nearly all of the I
(approximately 500 A) to go into charging C
in volts per second. I
of the next clock cycle. If the current limit condition is
removed, RST will be gradually discharged to ground,
and normal operation resumes as shown in Figure 6.
1.25V
2.5V
V(PIN 20)
V(PIN 12)
+
–
2.5V
1V
RST
+
–
. This current charges the reset capacitor C
Figure 6. I
Waveforms During Load Surge.
Q
PWM CYCLE
TERMINATE
R
S
I
1
RST
RST
V+
LIM
CLOCK
dv
dt
should be very large (in the order
will be turned off at the beginning
UNDER-VOLTAGE
and Resulting RC
LOCKOUT
500
C
RST
OUTPUT
INHIBIT
A
RST
ML4828
RST
RST
at a rate of:
current
RST
(11)
.
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