at73c224-h ATMEL Corporation, at73c224-h Datasheet
at73c224-h
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at73c224-h Summary of contents
Page 1
... The four power supplies are named: BOOST1, BUCK2, LDO3 and LDO4. Table 1-1 lists the different devices available in the AT73C224-x series. Power Management and Analog Companions (PMAAC) AT73C224-A AT73C224-B AT73C224-C AT73C224-D AT73C224-E AT73C224-F AT73C224-G AT73C224-H 4x Channels Power Supply: DC/DC BOOST DC/DC BUCK . 2x LDOs RTC 6266A–PMAAC–08-Sep-08 ...
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... BUCK2 = 1. LDO3 = 1. BOOST11 = 5.2V AT73C224 LDO4 = 3. LDO3 = BUCK2 = 1.8V AT73C224 LDO4 = 2. LDO3 = 2. LDO4 = 2.8V AT73C224 BUCK2= 1.8V 3- LDO3 = 2. BOOST1 = 5.2V AT73C224 LDO4 = 3. LDO3 = 3V AT73C224 2 Section 5.2. Section 5.3. Management Mode Comments BOOST1 can be activated after Start-up Dynamic sequence by a user command. BOOST1 can be activated after Start-up Dynamic sequence by a user command ...
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... VDDIO Digital D1 Interface D2 (TWI / SPI) D3 PMC D4 Status POK Register ITB VBG VBG POR, VMON (Voltage Monitor) VDD0 LPVBG (Low power VBG AT73C224 VDD1 VSENSE1 BOOST1 VOUT DL1 3.3V-5.2V ILOAD 1A VO1 VDD2 P BUCK2 SW2 VOUT 0.9V-3.4V ILOAD N 500 mA GND2 VO2 GND/AVSS OSC 900kHz ...
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... Pinout Table 3-1. AT73C224 Pinout Pin Name I/O Pin # VO3 O 1 VDD3 PS 2 GNDANA PS 3 VCAPP I/O 4 VINT PS 5 VDD0 PS 6 VCAPN I/O 7 VBG O 8 VDD2 PS 9 VBAT_LDORTC PS 10 VO2 POK O 14 ITB/RDY I/O 15 SW2 O 16 GND2 PS 17 VO1 I 18 DH1 O 19 ...
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... VO4 R1 VDD4 VDD1 VSENSE1 DL1 DH1 nc VO1 GND2 GND/AVSS Die Paddle Pushbutton L2 VO2 C2 C16 Table 4-1. AT73C224 LDO3 = 2.7V (AUX ADC, PLL) LDO4 = 2.8V VDDIO V BAT VO1 Microcontroller C1 Q1 USB HOST BOOST1 = 5V transceiver (VBUS USB) USB HOST transceiver BUCK2 = 1.8V VCORE POK ...
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... Battery 4.2V In the Application Schematic 2, the AT73C224-B is used: the BOOST (VO1) supplies the “VBUS” of one USB transceiver and supplies also LDO3 and LDO4. The BUCK(VO2) supplies the digital core of the microcontroller and the LDOs supply the I/Os and Analog cells, such as auxiliary ADC or PLL. ...
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... BAT C12 VO4 R1 VDD4 VDD1 VSENSE1 DL1 DH1 nc VO1 GND2 GND/AVSS Die Paddle L2 BUTTON VO2 C2 C16 Table 4-1. AT73C224 BOOST1 = 3.3V Analog Cells LDO4 = 1.8V VDDIO V BAT C6 D1 C15 L1 VO1 Microcontroller BOOST1 = 3.3V BUCK2 = 1.2V VCORE POK ITB/RDY SPI / TWI ...
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... C3 C5, C7, C8, C9, C11, C13 C10 C12, C14 C15 C16 L1 L1, L3 (in SEPIC config (can be printed on the board (Cu line)) R2 AT73C224 8 External Components Reference Tantalum TPS Case B Tantalum TPS Case A GRM155R60J225ME15 C1005X5R0J225MT GRM21BR60J226ME39 C2012X5R0J226MT GRM155R60J105KE19 C1005X5R0J105KT GRM155R61A104KA01 C0603X5R0J104KT GRM155R60J474KE18 C1005X5R1A474KT ...
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... Detailed Description The AT73C224 family of Power Management Units with four power supplies and an ultra low-power Real-time Clock. By choosing a specific ordering code “x” from different automatic start-up sequences and management modes can be selected. The start-up sequence includes the order of power-on, as well as the default value of the power ...
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... Static Mode In Static mode, the Power-off condition between the following conditions: main battery lower than 2.8V or electrical default in the DC/DC (short-circuit). When Power-off condition occurs, POK signal is cleared, then the AT73C224-x device waits for the signal ITB/RDY to shut down all power supplies. 5.2.2.2 ...
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... BOOST1 User Command: . AT73C224-A: Through Dynamic mode (using TWI or SPI) . AT73C224-F: Through Static mode (using D1 pin) 6266A–PMAAC–08-Sep-08 illustrates the complete automatic start-up sequence of the AT73C224-A and Figure 5-2 illustrates the automatic start-up sequence of the other 30 ms min 36 ms typ. ...
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... LDO3 (Default value: 1.8V) BOOST1 User Command: . AT73C224-D: Through Dynamic mode (using TWI or SPI) BUCK2 User command: . AT73C224-E: Through Dynamic mode (using TWI or SPI) . AT73C224-H: Through Static mode (using D2 pin) LDO4 (Default value: 3.3V) LDO3 (Default value: 3V) BOOST1 (Default value: 5.2V) AT73C224 12 ...
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... Digital Control and Protocol The AT73C224-x family offers a choice of devices in static mode or dynamic mode (see 1 on page between SPI or TWI is done at start-up via the D4 pin (see 5.3.1 Static Mode When the AT73C224-x is established in Static Mode, the digital interface signals D4, directly drive the enable of the four supplies. During start-up, these enable signals are driven by the internal state machine ...
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... For the devices of the AT73C224-x family that work in dynamic mode, supply management can be performed by the SPI or TWI digital interface. Selection between the two digital interfaces is done through D4 pin when the AT73C224-x is enabled. Pin digital input pin that features a controllable pull-up resistor with active low control signal. When the AT73C224-x starts, the pullup is disabled until a push button event is detected ...
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... SPI Operation When SPI mode is selected, the control interface to the AT73C224-x chip is a 4-wire interface modeled after commonly available microcontroller and serial-peripheral devices. The interface consists of a serial clock (SCK), chip select (SCS), serial data input (SDI) and serial data output (SDO) ...
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... SDI is a don't care during the data portion of read operations. During write operations, data is driven into the AT73C224-x via the SDI pin, MSB first. The SDO pin will remain in high imped- ance during write operations. Data always transitions with the falling edge of the clock and is latched on the rising edge ...
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... TWI Operation The TWI interface allows a microcontroller to proceed to read or write accesses to the internal registers of the AT73C224-x. Unlike the SPI, the TWI operation is based on a standard which defines a data-link layer and an addressing scheme. The TWI implementation used in the AT73C224-x conforms to this standard, with the following restrictions: • ...
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... Enables the interrupts globally. The ITB pin will toggle either the Write 10000000 in IRQ_EN RTC or the power monitor requests an interrupt. Write 00000001 in IRQ_DIS Disables the RTC interrupt. The power failure interrupt remains active. AT73C224 Acknowledge N = Not Acknowledge ADDR = Device Address ...
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... ITB/RDY). In this register, each potential interrupt source has a bit which indicates responsible for triggering the request. Once the source is identified, the microcontroller performs the handling routine in an application- dependant manner. It then needs to acknowledge the interrupt source to avoid being interrupted again for the same reason. 6266A–PMAAC–08-Sep-08 AT73C224 19 ...
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... ADDR: Reads the TWI address currently in use. This field can be used to check the connectivity of the TWI identify the AT73C224-x device. When ALT bit is 0, ADDR contains the alternate address (0x48). When ALT is 1, ADDR contains the default address (0x49). ...
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... Low effect. 1: the button low interrupt is enabled. • High effect. 1: the button high interrupt is enabled. 6266A–PMAAC–08-Sep- – – – – – – AT73C224 – HIGH LOW – HIGH LOW ...
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... SHUTDN Access Type: Write-only Address: 0x07 7 6 – – A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access effect. 1: shutdown the whole chip. AT73C224 – – – – ...
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... A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access. • EN: Writing starts the BOOST/SEPIC converter. Writing stops the BOOST/SEPIC converter. (*): Default value depends on the chosen AT73C224-x device (see 6266A–PMAAC–08-Sep- – ...
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... At the startup recommended to put 1 Amp over current threshold in order not to generate a reset of the product. AT73C224 – – ISHORT 6266A–PMAAC–08-Sep-08 ...
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... Default value depends on the chosen AT73C224-x device (see than the supply of the cell (VDD1). 6266A–PMAAC–08-Sep- [5:0] V [V] OUT OUT 010101 3 ...
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... EN: Writing starts the BUCK converter. Writing stops the BUCK converter. (*): Default value depends on the chosen AT73C224-x device (see • BYP: Writing BYP to 1 puts the BUCK2 output voltage to VDD2. Writing BYP to 0 configures the BUCK2 in Normal operation (default). ...
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... MODE: Selects the PWM pulse skipping mode. MODE Operation 00 Auto 01 PWM 10 Pulse skipping 11 Pass-through • SLIM: Selects the power-up mode. 0: current limitation. 1: slow start. 6266A–PMAAC–08-Sep- MODE AT73C224 ISHORT ...
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... OUTZ: Defines the state of the voltage output when the converter is off. 0: the output is forced to ground. 1: the output is left floating (Hz). AT73C224 28 6266A–PMAAC–08-Sep-08 ...
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... Default value depends on the chosen AT73C224-x device (see 6266A–PMAAC–08-Sep- – V [4:0] V [V] OUT OUT 10000 1.28 10001 1.42 10010 1.56 10011 1.7 10100 1.86 10101 2.00 10110 2.14 10111 2.29 11000 2.43 11001 2 ...
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... A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access. • EN: Writing starts the LDO3 regulator. Writing stops the LDO3 regulator. (*): Default value depends on the chosen AT73C224-x device (see 6.2.8 LDO3 Configuration Register Register Name: ...
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... Selects the output voltage of the regulator following the table below. V [3:0] V [V] OUT OUT 1000 1.3 0000 1.5 0001 1.6 0010 1.7 0011 1.8 0100 2.5 0101 2.6 0110 2.7 0111 2.8 1001 3.3 1010 4.9 others – (*): Default value depends on the chosen AT73C224-x device (see 6266A–PMAAC–08-Sep- – – Section AT73C224 2 1 VOUT(*) 5.2 ...
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... A minimum of 3 clock cycles of 15 kHz clock must be waited after any write operation before doing a new register access. • EN: Writing starts the LDO4 regulator. Writing stops the LDO4 regulator. (*): Default value depends on the chosen AT73C224-x device 6.2.11 LDO4 Configuration Register Register Name: ...
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... Selects the output voltage of the regulator following the table below. V [3:0] V [V] OUT OUT 1000 1.3 0000 1.5 0001 1.6 0010 1.7 0011 1.8 0100 2.5 0101 2.6 0110 2.7 0111 2.8 1001 3.3 1010 4.9 others – (*): Default value depends on the chosen AT73C224-x device (see 6266A–PMAAC–08-Sep- – – 0 Section AT73C224 2 1 VOUT(*) 1 1 5.2 ...
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... BOOST/SEPIC1. • PG2 power good condition on BUCK2. 1: the power good condition has been met on BUCK2. • PF2 power failure condition on BUCK2. 1: the power failure condition has been met on BUCK2. AT73C224 PF2 PG2 – ...
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... PF1 effect. 1: clears PF1 in the PMU_SR. • PG2 effect. 1: clears PG2 in the PMU_SR. • PF2 effect. 1: clears PF2 in the PMU_SR. 6266A–PMAAC–08-Sep- PF2 PG2 – – – AT73C224 PF1 PG1 SHORT1 – – – 35 ...
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... BOOST/SEPIC1 is enabled. • PF1 effect. 1: the power fail interrupt of BOOST/SEPIC1 is enabled. • PG2 effect. 1: the power good interrupt of BUCK2 is enabled. • PF2 effect. 1: the power fail interrupt of BUCK2 is enabled. AT73C224 PF2 PG2 – – ...
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... BOOST/SEPIC1 is disabled. • PG2 effect. 1: the power good interrupt of BUCK2 is disabled. • PF2 effect. 1: the power fail interrupt of BUCK2 is disabled. 6266A–PMAAC–08-Sep- PF2 PG2 – – – AT73C224 PF1 PG1 SHORT1 – – – 37 ...
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... BOOST/SEPIC1 is disabled. 1: the power fail interrupt of BOOST/SEPIC1 is enabled. • PG2: 0: the power good interrupt of BUCK2 is disabled. 1: the power good interrupt of BUCK2 is enabled. • PF2: 0: the power fail interrupt of BUCK2 is disabled. 1: the power fail interrupt of BUCK2 is enabled. AT73C224 PF2 PG2 – ...
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... Writing to 1 globally enables all the interrupt sources that had been previously enabled individually. The interrupt setting for each source is restored. Writing 0 has no effect. 6266A–PMAAC–08-Sep- DC2 DC1 – – – AT73C224 PWR PB RTC – – – 39 ...
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... Writing 0 has no effect. • DC2: Disables the BUCK2 interrupt when written to 1. Writing 0 has no effect. • ALL: Writing to 1 globally disables all the interrupt sources. The individual setting of each interrupt source is saved. Writing 0 has no effect. AT73C224 DC2 DC1 – ...
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... BOOST/SEPIC1 interrupt is unmasked. • DC2: 0: the BUCK2 interrupt is masked. 1: the BUCK2 interrupt is unmasked. • ALL: 0: the interrupt sources are globally masked. 1: the interrupt sources are globally unmasked. 6266A–PMAAC–08-Sep- DC2 DC1 – AT73C224 PWR PB RTC ...
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... PWR: 1: signals a pending interrupt request from the power monitor. • DC1: 1: signals a pending interrupt request from the BOOST/SEPIC1. • DC2: 1: signals a pending interrupt request from the BUCK2. AT73C224 DC2 DC1 – ...
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... Selects the type of event to cause CALEV to change in RTC_SR. every 00 week change Monday every 1st of 01 month change each month 10 every 1st of year change 11 January 6266A–PMAAC–08-Sep- TIMEVSEL – time 00:00:00 at time 00:00:00 at time 00:00:00 AT73C224 – UPDCAL UPDTIM ...
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... RST: RST = 0, Normal Operation RST=1, Reset the RTC 6.4.3 RTC Mode Register Register Name: RT_MR Access Type: Read/Write Address: 0x44 7 6 – – • HRMOD: 0: 24-hour mode. 1: 12-hour mode. AT73C224 – – – – – – – – ...
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... This field must not be written unless the time counter has been stopped. • AMPM: This bit controls/reflects the AM/PM indicator in 12-hour mode. 0: AM. 1: PM. 6266A–PMAAC–08-Sep- SEC MIN AT73C224 HOUR ...
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... The range 12, encoded in BCD. The lowest four bits encode the units, the higher bits encode the tens. • DAY: The range is 1-7 and represents the day of the week. The relationship between the coding of this field and the actual day of the week, is user-defined. Especially, writing to this bit has no effect on the date counter. AT73C224 ...
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... DAY 1 0 • DATE: The range 31, encoded in BCD and represents the day of the month. The lowest four bits encode the units, the higher bits encode the tens. 6266A–PMAAC–08-Sep- AT73C224 DATE ...
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... Register Name: RT_MINA Access Type: Read/Write Address: 0x51 7 6 MINEN 0 0 • MIN: This field is the alarm field corresponding to the BCD-encoded minute counter. • MINEN 0: the minute-matching alarm is disabled. 1: the minute-matching alarm is enabled. AT73C224 SEC MIN ...
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... This field is the alarm field corresponding to the BCD-encoded hour counter. • AMPM: This field is the alarm field corresponding to the BCD-encoded hour counter. • HOUREN 0: the hour-matching alarm is disabled. 1: the hour-matching alarm is enabled. 6266A–PMAAC–08-Sep- AT73C224 2 1 HOUR ...
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... Read/Write Address: 0x56 7 6 DATEEN – 0 • DATE: This field is the alarm field corresponding to the BCD-encoded day of the month counter. • DATEEN: 0: the day of the month-matching alarm is disabled. 1: the day of the month-matching alarm is enabled. AT73C224 – ...
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... The calendar event is selected in the CALEVSEL field in RTC_CR and can be any of the following events: week change, month change, or year change. 6266A–PMAAC–08-Sep- – CALEV TIMEV 0 0 AT73C224 SEC ALARM ACKUPD ...
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... ALARM bit RTC_SR. • SECCLR effect. 1: clears the SEC bit RTC_SR. • TIMCLR effect. 1: clears the TIMEV bit RTC_SR. • CALCR effect. 1: clears the CALEV bit RTC_SR. AT73C224 – CALCLR TIMCLR ...
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... TIMEN effect. 1: the selected time event interrupt is enabled. • CALEN effect. 1: the selected calendar event interrupt is enabled. 6266A–PMAAC–08-Sep- – CALEN TIMEN 0 0 AT73C224 2 1 SECEN ALREN ACKEN ...
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... SECDIS effect. 1: the second periodic interrupt is disabled. • TIMDIS effect. 1: the selected time event interrupt is disabled. • CALDIS effect. 1: the selected calendar event interrupt is disabled. AT73C224 – CALDIS TIMDIS ...
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... CAL: 0: the selected calendar event interrupt is disabled. 1: the selected calendar event interrupt is enabled. 6266A–PMAAC–08-Sep- – CAL TIM 0 0 AT73C224 SEC ALR ACK ...
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... NVTIMA invalid data has been detected in the time alarm registers. 1: invalid data has been detected. • NVCALA invalid data has been detected in the calendar alarm registers. 1: invalid data has been detected. AT73C224 – – ...
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... This is a stress rating only and functional operation of the device at these or other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. Condition AT73C224 Min Max Unit -40 85 ° ...
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... RTC (dig + oscillator 32 kHz) - supply: vbackup pin Main Battery plugged in and higher than 2.8V Backup battery present (and charged) . Power supplies off (BOOST1, BUCK2, LDO3, LDO4) Stand by . Running: RTC, LDO_RTC - supply: vbat_ldortc POR, LPBG, VMON - supply: vdd0 pin AT73C224 58 Conditions when applicable Min Typ Max Unit 1 ...
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... BST_CLR register (@10 BST_CFG register (@11 VDD1 = 2.8V, VO1 = 3. VDD1 = 3.3V, VO1 = 5. load peak-to-peak VO1 = 5.2V O Bandwidth = 20 MHz VDD1: 2 VO1 = 5.2V O VDD1: 3. 100 mA to 900 VO1 = 5.2V AT73C224 Min Typ Max Unit 2.8 3.6 5.25 V 400 900 1400 kHz 1 A 3.2 5.2 V -10 -10 ...
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... BOOST1: Typical Characteristics Figure 7-1. Efficiency BOOST1 - VO1 = 5V - 100 0.01 AT73C224 60 0.1 Iload (A) VDD1 = 4.2V VDD1 = 3.6V VDD1 = 3V VDD1 = 2.8V 1 6266A–PMAAC–08-Sep-08 ...
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... Figure 7-2. Load Regulation BOOST1 - VO1 = 5V - 5.32 5.3 5.28 5.26 5.24 5.22 5.2 5.18 5.16 5.14 5.12 5.1 5.08 5.06 5.04 5.02 0 0.1 0.2 The BOOST1 cell can be implemented using proper external components. (See “Application Schematic 3: BOOST in SEPIC Configuration 6266A–PMAAC–08-Sep-08 0.3 0.4 0.5 0.6 Iload (A) AT73C224 VDD1 = 4.2V VDD1 = 3.6V VDD1 = 3V VDD1 = 2.8V 0.7 0.8 0.9 1 (BUCK/BOOST)”.) Figure 4-3 61 ...
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... Pulse-Skipping mode (light load PWM mode (high load). In dynamic mode, the user can select PWM or PSK mode, using the bits 4 and 5 of the BCK_CFG register (see Sec- tion 6 Register Tables). Note that the Automatic mode should not be used for output voltages below 1.8V. AT73C224 62 Conditions PWM mode BCK_VOLT register (@15) - Step 100mV VDD2 > ...
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... Efficiency VO2 = 3.3V - Manual Mode: PSK/PWM 100 95 90 VDD2 = 4. VDD2 = PWM 45 VDD2 = 4.2V 40 PSK VDD2 = 0.1 1 0.001 Efficiency VO2 = 3.3V - Automatic Mode 100 VDD2 = 4.2V 80 VDD2 = 0.001 0.1 1 AT73C224 PWM PSK 0.01 0.1 Iload (A) PWM PSK 0.01 0.1 Iload (A) 0.01 0.1 1 Iload ( ...
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... BUCK2: Load Regulation of VO2 Figure 7-4. Load Regulation Load Regulation: VO2 = 0.9V (PWM mode) 0.93 0.92 0.91 VDD2 = 2.8V 0.9 VDD2 = 3.6V 0.89 VDD2 = 4.2V 0.88 0.87 VDD2 = 5V 0.86 0.85 0 0.05 0.1 0.15 0.2 0.25 I load (A) Load Regulation: VO2 = 1.8V (PWM Mode) 1.84 VDD2 = 2.8V 1.82 1.8 VDD2 = 3.6V 1.78 VDD2 = 4.2V 1.76 1.74 VDD2 = 5.5V 1.72 0 0.05 0.1 0.15 0.2 0.25 I load (A) AT73C224 64 1.23 1.22 1.21 1.2 1.19 1.18 1.17 1.16 1.15 0.3 0.35 0.4 0.45 0.5 0 0.05 3.3 3.29 3.28 3.27 3.26 3.25 3.24 3.23 3.22 0 0.05 0.3 0.35 0.4 0.45 0.5 Load Regulation: VO2 = 1.2V (PWM mode) VDD2 = 2.8V VDD2 = 3.6V VDD2 = 4.2V VDD2 = 5.5V 0.1 0.15 0.2 0.25 0.3 0.35 0.4 I load (A) Load Regulation: VO2 = 3 ...
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... LDO4_CFG@1A) No load 2.8V < VDD3 < 5.25V, full load 10 mA <I <100 mA LOAD In RF mode Bandwidth: [22 - 80kHz mode: I =100mA, 100 Hz LOAD I =100mA, 1kHz LOAD I =100mA, 10kHz LOAD I =100mA, 100kHz LOAD AT73C224 Section 6.2.8 ”LDO3 Configuration Register”). Min Typ Max 2.8 3.6 5.25 0 200 0 100 1.3 3 100 10 ...
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... Shown below is VO3 Ripple (same as VO4) in response to a load current pulse from 200 mA. Channel 2: VO3 = 1.8V and VO3 = 3.3V (50mV/div) Channel 1: Iload = 200 mA (100 mA/div) AT73C224 66 3.276 3.275 3.274 3.273 3.272 3.271 VDD3 = 2.8V 3.27 3.269 3.268 3.267 3.266 3 ...
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... The RTC oscillator is suited to work with a 32.768 kHz crystal oscillator and generates the 32.768 kHz clock for the RTC. The RTC block provides seconds, minutes, hours, days, date, month, and year information. RTC time data is stored into a register that can be accessed via the AT73C224-x device serial interface. 6266A–PMAAC–08-Sep-08 Figure 7-6 ...
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... It may be necessary to add external capacitors on “xin” and “xout” to ground in special cases, for example, to exactly set the frequency or for crystals with a load capacitance superior to 6 pF. The “clock” output is low during standby. “xin” and “xout” must not be used to drive other circuitry. AT73C224 68 Conditions Vbat_ldortc present ...
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... VINT One external capacitor (47 0nF) is necessary on VINT pin for functionality of the internal LDO supply. This voltage should not be used by the user. 6266A–PMAAC–08-Sep-08 AT73C224 69 ...
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... Package Drawing Figure 8-1. R-QFN032_H AT73C224 70 QFN 32-lead Package Drawing (all dimensions in millimeters) 6266A–PMAAC–08-Sep-08 ...
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... Revision History Doc. Rev. Comments 6266A First issue. 6266A–PMAAC–08-Sep-08 AT73C224 Change Request Ref. 71 ...
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... AT73C224 72 6266A–PMAAC–08-Sep-08 ...
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... Automatic Start-up Sequences and Shut-down ...............................................10 5.3 Digital Control and Protocol .............................................................................13 6.1 System Registers ............................................................................................20 6.2 PMU Registers ................................................................................................23 6.3 Interrupt Registers ...........................................................................................39 6.4 RTC Registers .................................................................................................43 7.1 Absolute Maximum Ratings .............................................................................57 7.2 Recommended Operating Conditions .............................................................57 7.3 Digital I/Os .......................................................................................................58 7.4 Current Consumption Versus Modes ..............................................................58 7.5 BOOST1: Step-up Converter ...........................................................................59 7.6 BUCK2: Step-down Converter .........................................................................62 7.7 LDO3 & LDO4 .................................................................................................65 7.8 Real-time Clock (RTC) ....................................................................................67 7.9 VINT ................................................................................................................69 AT73C224 i ...
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... AT73C224 ii 6266A–PMAAC–08-Sep-08 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Europe Le Krebs ...