lm95172q National Semiconductor Corporation, lm95172q Datasheet - Page 18
lm95172q
Manufacturer Part Number
lm95172q
Description
Digital Temperature Sensor In Die Form With ?1?c Accuracy From 130?c To 160?c
Manufacturer
National Semiconductor Corporation
Datasheet
1.LM95172Q.pdf
(24 pages)
www.national.com
1.7.4 T
(Read/Write) Pointer Address: 82h (Read); 02h (Write)
Bit <15:5>: Upper-Limit Temperature byte. If the measured temperature, stored in the temperature register, exceeds this user-
programmable temperature limit, the OVERTEMP pad will assert and the T
Bit <4:0>: Reserved. Returns all zeroes when read.
Reset State: 4880h (+145°C)
Reset Conditions: Upon Power-on Reset.
1.7.5 T
(Read/Write) Pointer Address: 83h (Read); 03h (Write)
Bit <15:5>: Lower-Limit Temperature byte. If the measured temperature that is stored in the temperature register falls below this
user-programmable temperature limit, the OVERTEMP pad will not assert and the T
set to "1".
Bit <4:0>: Reserved. Returns all zeroes when read.
Reset State: 4600h (+140°C)
Reset Conditions: Upon Power-on Reset.
1.7.6 MFGID: Manufacturer, Product, and Step ID Register
(Read Only) Pointer Address: 87h
Bit <15:8>: Manufacturer Identification Byte. Always returns 80h to uniquely identify the manufacturer as National Semiconductor
Corporation.
Bit <7:4>: Product Identification Nibble. Always returns 30h to uniquely identify this part as the LM95172Q.
Bit <3:0>: Die Revision Nibble. Returns 0h to uniquely identify the revision level as zero.
Reset State: 8030h
Reset Conditions: Upon Power-on Reset.
HIGH
LOW
: Lower Limit Register
: Upper Limit Register
Sign
Sign
D15
D15
D15
1°C
1°C
D7
D7
D7
1
0
128°C
128°C
0.5°C
0.5°C
D14
D14
D14
D6
D6
D6
0
0
0.25°C
0.25°C
64°C
64°C
D13
D13
D13
D5
D5
D5
0
1
32°C
32°C
D12
D12
D12
D4
D4
D4
0
1
18
16°C
16°C
D11
D11
D11
D3
D3
D3
0
0
HIGH
Reserved
Reserved
flag in the Control/Status register will be set to "1".
D10
D10
D10
8°C
8°C
D2
D2
D2
0
0
LOW
flag in the Control/Status register will be
4°C
4°C
D9
D1
D9
D1
D9
D1
0
0
2°C
2°C
D8
D0
D8
D0
D8
D0
0
0