a8291 Allegro MicroSystems, Inc., a8291 Datasheet - Page 10

• Manufacturer Part Number: a8291
• Description: A8291 Single Lnb Supply And Control Voltage Regulator
• Manufacturer: Allegro MicroSystems, Inc.

A8291
tion. If the Read/Write bit is high, the master reads the contents of
register 1, followed by register 2 if a further read is performed. If
the Read/Write bit is low, the master writes data to one of the two
Control registers. Note that multiple writes are not permitted. All
write operations must be preceded with the address.
ter to determine if the slave device is responding to its address
and data, and it is used by the slave when the master is reading
data back from the slave. When the A8291 decodes the 7-bit ad-
dress field as a valid address, it responds by pulling SDA low
during the ninth clock cycle.
low during the clock cycle that follows the data byte, in order to
indicate that the data has been successfully received. In both cas-
es, the master device must release the SDA line before the ninth
clock cycle, in order to allow this handshaking to occur.
same way as in the data write sequence, and then retains control
of the SDA line and send the data from register 1 to the master.
On completion of the eight data bits, the A8291 releases the SDA
line before the ninth clock cycle, in order to allow the master to
acknowledge the data. If the master holds the SDA line low dur-
ing this Acknowledge bit, the A8291 responds by sending the
data from register 2 to the master. Data bytes continue to be sent
to the master until the master releases the SDA line during the
Acknowledge bit. When this is detected, the A8291 stops sending
data and waits for a stop signal.
Interrupt Request
is an open-drain, active-low output. This output may be connect-
The Read/Write bit is used to determine the data transfer direc-
The Acknowledge bit has two functions. It is used by the mas-
During a data write from the master, the A8291 also pulls SDA
During a data read, the A8291 acknowledges the address in the
The A8291 also provides an interrupt request pin, IRQ, which
Figure 3. I
2
C™ Interface. Read sequences after interrupt request.
SDA
SCL
IRQ
Fault
Event
Single LNB Supply and Control Voltage Regulator
Start
0
1
0
2
0
3
Address
1
4
0
5
Read after Interrupt
A1
6
A0
7
R
1
8
ed to a common IRQ line with a suitable external pull-up and can
be used with other I
from the master controller.
recognizes a fault condition, or at power-on, when the main sup-
ply, V
operating conditions. It is only reset to inactive when the I
master addresses the A8291 with the Read/Write bit set (caus-
ing a read). Fault conditions are indicated by the TSD, VUV, and
OCP bits, and are latched in the Status register. See the Status
register section for full description.
terrupt. All these bits are continually updated, apart from the DIS
bit, which changes when the LNB is either disabled, intentionally
or due to a fault, or is enabled.
slaves connected to the interrupt line in sequence, and then reads
the status register to determine which device is requesting atten-
tion. The A8291 latches all conditions in the Status register until
the completion of the data read. The action at the resampling
point is further defined in the Status Register section. The bits
in the Status register are defined such that the all-zero condition
indicates that the A8291 is fully active with no fault conditions.
does not respond to any requests until the internal logic supply
V
point, the IRQ output goes active, and the VUV bit is set. After
the A8291 acknowledges the address, the IRQ flag is reset. After
the master reads the status registers, the registers are updated with
the VUV reset.
AK
9
REG
The IRQ output becomes active when either the A8291 first
The DIS, PNG, CAD and TDET status bits do not cause an in-
When the master recognizes an interrupt, it addresses all
When V
D7
IN
has reached its operating level. Once V
D6
, and the internal logic supply, V
D5
Status Register 1
IN
is initially applied, the I
D4
D3
2
C™-compatible devices to request attention
D2
D1
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
D0
NAK
Reload
Status Register
Stop
2
C™-compatible interface
REG
, reach the correct
REG
has reached this
2
C™
10