sc473mltrt Semtech Corporation, sc473mltrt Datasheet - Page 11

• Manufacturer Part Number: sc473mltrt
• Description: Sc473 Single-phase Single Chip Graphics Core Power Supply
• Manufacturer: Semtech Corporation

For the SC473 cold start-up, V5 must rise above its under-
voltage lockout (UVLO) threshold (4.4V typ.) The EN signal
may go high either before UVLO or after (preferred). The
DAC drives 120μA (typical) into the soft-start capacitor on
the SS pin. The SS pin and DAC rise slowly until the VID(4:0)
When the voltage hits the lower PWRGD threshold, PWRGD
goes high, and start-up is complete.
In a normal shutdown, the EN signal is driven low, the TG
and BG signals are driven low, tri-stating the power chains.
An approximately 10Ω FET on the FB+ signal discharges
Vcore slowly and prevents normal amounts of leakage from
pulling Vcore high. The DAC is discharged to zero, but the
power regulation circuitry is inactive, and PWRGD is low.
DAC Description:
A +/-0.85% 5-bit digital-to-analog converter (DAC) serves as
the programmable reference source of the Core Compara-
tor. Programming is accomplished by logic voltage levels
applied to the DAC inputs. The VID code vs. the DAC output
is shown in Table 1. The fi ve voltage identifi cation pins are
used to support automatic selection of V
DAC Slew Rate Control:
The DAC also has integrated slew-rate control with to
charge and discharge the soft-start capacitor. All operat-
ing voltage transitions including soft-start use the 120μA
source to charge the soft-start capacitor.
Power Supply Protection:
The UVLO circuit consists of a comparator that monitors
the input supply voltage level, V5. The SC473 is in UVLO
mode when its supply voltage has not ramped above the
upper threshold or dropped below the lower threshold. The
output of the UVLO comparator turns on or off the internal
bias, enables or disables the SC473 output, and initiates
or resets the soft-start timer.
The OVP circuit of SC473 monitors the processor core V
voltage for an over-voltage condition. If the FB voltage is
200mV greater than the DAC voltage (i.e., out of the pow-
ergood window), the SC473 will latch off and hold the low-
side driver on permanently. Either the power or EN must
be recycled to clear the latch. The latch is disabled
© 2006 Semtech Corp.
Start-Up and Soft-Off Sequences:
POWER MANAGEMENT
Applications Information (Cont.)
OUT
voltages.
OUT
11
safety, the latch is enabled if the FB voltage exceeds 1.7V
even during VID transitions.
The device will be disabled and latched off when the
internal junction temperature reaches approximately
160°C. Either the power or EN must be recycled to clear
the latch.
Power Monitor:
The SC473 adds a power monitor feature to accurately
predict the graphics CPU power consumption. The power
monitor output depends on the current sensing methodol-
ogy used. The following diagram and equation predict the
ideal PMON output.
Similar exercise can be done for R-SENSE confi guration
as shown below:
during soft-start and VID/DeeperSleep transitions. For
DC Voltage Between Two Terminals is:
DRN
Req
=
V
two terminals is
Between these
(TH2
DCR
R
DCR
I
Voltage
LOAD
16.2k
=
R27
Veq
I
LOAD
+
R24)(R28
PMON_Ideal
x R
L1
Power Monitor Implementation for SC473 (DCR Sense)
Veq
DCR
IR33
18.2k
33k
(VDCR
TH2
R24
+
R30
VR33
Veq
+Vcc_core
+
Combination of Resistors
V
C54
x
R33)
(R28
R33
shown in the box
R30
Req)
IR33
R28
Req = Parallel
Vcc_core
(TH2
R30
R33
(Req
+
R33)
R24
R27)
28.5
I
+
R33
www.semtech.com
R28
SC473
R33
5k
+
R30
CS+
CS-
+
R33)
V
R33