ip2021c International Rectifier Corp., ip2021c Datasheet

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ip2021c

Manufacturer Part Number
ip2021c
Description
Synchronous Buck Dual Channel Power Block
Manufacturer
International Rectifier Corp.
Datasheet
Features
Applications
Typical Application (Dual Output)
www.irf.com
iP2021CTRPbF
iP2021CPbF
Description
Package
60A Multiphase building block
No derating up to T
Integrated 6V LDO
Operation up to 1 MHz
Bi-directional current flow
Under Voltage Lockout
Optimized for low power loss
LGA interface
11mm x 7.65mm outline
Multi-phase Architectures
Low Duty-Ratio, High Current
Microprocessor Power Supplies
High Frequency Low Profile DC-DC
Converters
Connection
Interface
LGA
LGA
PCB
= 95ºC
Integrated Power Semiconductors, Drivers, & Passives
Standard
Quantity
2000
10
8/13/2009
Description
The iP2021C is a fully optimized solution for
high current synchronous buck dual-phase or
dual output applications. Board space and
design time are greatly reduced because most
of the components required for both power
stages are integrated into a single 11mm x
7.7mm power block. The only additional
components required for a complete converter
are a PWM controller, the output inductors,
and the input and output capacitors.
iPOWIR
innovative board space saving solution for
applications requiring high power densities.
iPOWIR
optimized internally for layout, heat transfer
and component selection.
Dual Channel Power Block
technology
technology
Synchronous Buck
iP2021CPbF
offers
solutions
PD-97414
designers
are
1
also
an

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ip2021c Summary of contents

Page 1

... Dual Channel Power Block Integrated Power Semiconductors, Drivers, & Passives = 95ºC Description The iP2021C is a fully optimized solution for high current synchronous buck dual-phase or dual output applications. Board space and design time are greatly reduced because most of the components required for both power stages are integrated into a single 11mm x 7 ...

Page 2

... BLK DD IN1 Min Typ Max Units 11 (Note 8/13/2009 PD-97414 iP2021CPbF Conditions V A Current per channel 14V unless otherwise IN2 Conditions 12V, DD IN1 IN2 V = 1.3V 60A (outputs OUT OUT combined 1MHz, ...

Page 3

... Min Typ Max Units - µF 4.15 4.5 V 3.6 3.95 V 200 0 100 - mV - 100k - Ω 0 100 - mV - 100k - Ω 8/13/2009 PD-97414 iP2021CPbF Conditions – 14.5V DD -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC See Figure 8 for timing diagram 3 ...

Page 4

... Output Current (A) Figure 1 Power Loss Curve Case Temperature (º Safe Operating Area PCB Temperature (ºC) Figure 2 Safe Operating Area Curve 8/13/2009 PD-97414 iP2021CPbF 100 110 120 130 Tx 90 100 110 120 130 4 ...

Page 5

... V = 1.3V 1. 60A OUT F = 1MHz SW 0.50 1. 125ºC BLK 0.25 0.95 0.00 -0.25 0.90 -0.50 0.85 -0.75 -1.00 0.80 0.6 0 200 Figure 6 Normalized Power Loss vs. Switching Frequency 8/13/2009 PD-97414 iP2021CPbF V = 12. 60A OUT F = 1MHz 325nH 125ºC BLK 1.0 1.3 1.5 1.8 2.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 Output Voltage ( 12. 1. 60A OUT L = 325nH 125ºC ...

Page 6

... Power Loss Measurement Setup www.irf.com Figure 7 Power Loss Test Circuit 90% 10% t PDH Figure 8 Timing Diagram 8/13/2009 PD-97414 iP2021CPbF 10% 90% t PDL 6 ...

Page 7

... Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y-axis (Output Current). The point at which the horizontal line meets the Y-axis is the SOA continuous current. Figure 9 SOA Example, Continuous current  31A for T www.irf.com axis intercept to the SOA curve 100ºC & T PCB 8/13/2009 PD-97414 iP2021CPbF = 110ºC CASE 7 ...

Page 8

... SOA Procedure 1. Determine the maximum PCB and CASE temperature at the maximum operating current for each iP2021C 2. Use the normalized curves to obtain SOA temperature adjustments that match the operating conditions in the application 3. Then, add the sum of the SOA temperature adjustments to the T ...

Page 9

... SOA current is Case Temperature (º (5) ( PCB Temperature (ºC) axis intercept to the SOA curve. X axis by adding or subtracting the SOA adjustment X intercept point. X 8/13/2009 PD-97414 iP2021CPbF 90 100 110 120 130 (2) (4) Tx (1) 90 100 110 120 130 9 ...

Page 10

... FET is on and sync FET is off. When PWM is LOW, the sync FET is on and the control FET is off. When set to logic level high, internal circuitry of the device is enabled. When set to logic level low, the control and synchronous FETs are turned off. Supply voltage for internal circuitry 8/13/2009 PD-97414 iP2021CPbF 10 ...

Page 11

... Place as many vias around the Power pads (V • electrical and optimal thermal performance (see Figure 12). A minimum of three 10µF, X5R, 16V ceramic capacitors per phase of iP2021C are needed for • 28A operation at 1MHz. This will result in the lowest loss due to input capacitor ESR. ...

Page 12

... Figure 12 Top & Bottom Component and Via Placement (Topside, Transparent view down) www.irf.com iP2021CPbF 8/13/2009 PD-97414 12 ...

Page 13

... CONTROLLING DIMENSION: MILLIMETER. 4 LAND PAD OPENINGS. 8 VSW 2 5 PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE SOLDER RESIST OPENING. 6 BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE 9 10 VIN 2 PACKAGE BODY. 7 NOT TO SCALE. Figure 13 Mechanical Outline Drawing 8/13/2009 PD-97414 iP2021CPbF 5 C 1.66 [.065] 0.07 [.0027] C SIDE VIEW 13 ...

Page 14

... Figure 14 Tape and Reel Information 8/13/2009 PD-97414 iP2021CPbF 14 ...

Page 15

... Recommended Solder Paste Stencil Design The recommended reflow peak temperature is 260°C. The total furnace time is approximately 5 minutes with approximately 10 seconds at peak temperature. www.irf.com Figure 15 Solder Paste Stencil Design 8/13/2009 PD-97414 iP2021CPbF 15 ...

Page 16

... Part Marking www.irf.com Figure 16 Part Marking 8/13/2009 PD-97414 iP2021CPbF 16 ...

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