attiny22l ATMEL Corporation, attiny22l Datasheet - Page 7

• Manufacturer Part Number: attiny22l
• Description: 8-bit Microcontroller With 2k Bytes Of In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

Instruction Set Summary
Mnemonics
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBIW
SBC
SBCI
AND
ANDI
OR
ORI
EOR
COM
NEG
SBR
CBR
INC
DEC
TST
CLR
SER
BRANCH INSTRUCTIONS
RJMP
IJMP
RCALL
ICALL
RET
RETI
CPSE
CP
CPC
CPI
SBRC
SBRS
SBIC
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
Operands
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Rd
Rd,K
Rd,K
Rd
Rd
Rd
Rd
Rd
k
k
Rd,Rr
Rd,Rr
Rd,Rr
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
Description
Subtract two Registers
Subtract Immediate from Word
Logical AND Register and Constant
Logical OR Registers
Logical OR Register and Constant
One’s Complement
Clear Bit(s) in Register
Increment
Test for Zero or Minus
Clear Register
Indirect Call to (Z)
Compare
Compare with Carry
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Logical AND Registers
Exclusive OR Registers
Two’s Complement
Set Bit(s) in Register
Decrement
Set Register
Relative Jump
Indirect Jump to (Z)
Relative Subroutine Call
Subroutine Return
Interrupt Return
Compare, Skip if Equal
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
Operation
Rd
Rd
Rdh:Rdl
Rd
Rd
Rdh:Rdl
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
PC
PC
PC
PC
PC
PC
if (Rd = Rr) PC
Rd
Rd
Rd
if (Rr(b)=0) PC
if (Rr(b)=1) PC
if (P(b)=0) PC
if (R(b)=1) PC
if (SREG(s) = 1) then PC
if (SREG(s) = 0) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (N
if (N
if (H = 1) then PC
if (H = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (I = 1) then PC
if (I = 0) then PC
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
−
−
−
←
←
←
←
←
←
←
⊕
⊕
Rr
Rr
K
Rd + Rr
Rd + Rr + C
Rd
Rd
Rd
Rd
Rd
Rd
Rd v Rr
Rd v K
Rd
$FF
$00
Rd v K
Rd
Rd + 1
Rd
Rd
$FF
PC + k + 1
Z
PC + k + 1
Z
STACK
STACK
Rd
V= 0) then PC
V= 1) then PC
−
←
←
−
−
−
−
•
•
⊕
•
−
•
C
⊕
−
−
Rr
K
($FF
Rd
Rr
K
Rr
K
1
Rdh:Rdl + K
Rdh:Rdl
Rr
Rd
Rd
Rd
−
−
C
←
←
C
←
←
←
−
PC + 2 or 3
PC + 2 or 3
←
←
PC + 2 or 3
PC + 2 or 3
K)
PC + 2 or 3
←
←
←
←
←
←
←
←
←
←
←
←
←
←
PC + k + 1
PC + k + 1
−
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
K
←
←
PC + k + 1
PC + k + 1
←
←
PC + k + 1
PC + k + 1
Flags
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
I
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
#Clock
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1
1
2
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
4
4
1
1
1
7