at91sam7x256 ATMEL Corporation, at91sam7x256 Datasheet - Page 16
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at91sam7x256
Manufacturer Part Number
at91sam7x256
Description
Preliminary Summary
Manufacturer
ATMEL Corporation
Datasheet
1.AT91SAM7X256.pdf
(45 pages)
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7.4
16
Peripheral DMA Controller
AT91SAM7X512/256/128 Preliminary
• Embedded Flash Controller
• Handles data transfer between peripherals and memories
• Thirteen channels
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirements
• Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest):
– Embedded Flash interface, up to three programmable wait states
– Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required
– Key-protected program, erase and lock/unlock sequencer
– Single command for erasing, programming and locking operations
– Interrupt generation in case of forbidden operation
– Two for each USART
– Two for the Debug Unit
– Two for the Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for the Analog-to-digital Converter
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
wait states
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Transmit
Transmit
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Transmit
DBGU
USART0
USART1
SSC
ADC
SPI0
SPI1
DBGU
USART0
USART
SSC
SPI0
SPI1
6120ES–ATARM–08-Oct-07