at32ap7002 ATMEL Corporation, at32ap7002 Datasheet - Page 43

• Manufacturer Part Number: at32ap7002
• Description: Avr 32 32-bit Microcontroller
• Manufacturer: ATMEL Corporation

32054DS–AVR32–10/07
19. SPI disable does not work in SLAVE mode.
21. SCC - First Data transmitted after reset is not DATDEF.
21. MCI - False data timeout error DTOE may occur.
22. SDRAM - Self-refresh mode
23. SPI - No TX UNDERRUN flag available
PDC will continue to write data in the SPI_TDR (as TDRE keeps High) till its buffer is empty,
and all data written after the disable command is lost.
Fix/Workaround
Disable PDC, 2 NOP (minimum), Disable SPI. When you want to continue the transfer:
Enable SPI, Enable PDC.
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a Software Reset.
In the first frame transmitted, the first transmitted data that follows the frame synchro is 0,
not DATDEF. This happens when:
1. PDC is disabled
2. Reset the SSC
3. Configure the SSC with a transmit START condition different from CONTINUOUS
(START = 0)
4. DATDEF = 1
5. Enable the SSC in transmission.
This trouble only appears after a reset and it is only the first frame is affected.
Fix/Workaround
Use the PDC to fill the THR after the enable of the SSC and before the start of the frame.
If a small block (5 bytes) is read through the READ_SINGLE_BLOCK command (CMD17),
the flag NOTBUSY will be set and a false data timeout error DTOE occurs.
Fix/Workaround
None.
If Entry in Self-refresh mode is followed by SDRAM access and auto-refresh event, TRC tim-
ing is not checked for AUTO_REFRESH sequence.
Fix/Workaround
Set the value of TRAS field in user interface with TRC+1.
There is no TX UNDERRUN flag available, therefore in slave mode there is no way to be
informed of a character lost in transmission.
Fix/Workaround
PDC/PDCA transfers: None.
Manual transfers (no PDC and TX slave only): Read the RHR every time the THR is written.
The OVRS flag of the status register will track any UNDERRUN on the TX side.
AT32AP7002
43