c8051f410 Silicon Laboratories, c8051f410 Datasheet - Page 258
c8051f410
Manufacturer Part Number
c8051f410
Description
2.0 V, 32/16 Kb Flash, Smartclock, 12-bit Adc
Manufacturer
Silicon Laboratories
Datasheet
1.C8051F410.pdf
(270 pages)
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C8051F410/1/2/3
25.3.1. Watchdog Timer Operation
While the WDT is enabled:
•
•
•
•
•
•
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH5 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in PCA0CPL5 is loaded
into PCA0CPH5 (See Figure 25.10).
258
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2-CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 5 is forced into software timer mode.
Writes to the Module 5 mode register (PCA0CPM5) are disabled.
PCA0CPL5
C
D
L
I
W
D
T
E
PCA0MD
W
D
C
K
L
Figure 25.10. PCA Module 5 with Watchdog Timer Enabled
PCA0CPH5
C
P
S
2
Write to
C
P
S
1
C
P
S
0
C
E
F
8-bit Adder
Enable
Adder
Enable
Rev. 1.0
PCA0CPH5
Comparator
PCA0H
8-bit
Match
PCA0L Overflow
Reset
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