mc9s08rd60fj Freescale Semiconductor, Inc, mc9s08rd60fj Datasheet - Page 91

• Manufacturer Part Number: mc9s08rd60fj
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

00
3
01
BRCLR0
3
02
3
03
BRCLR1
3
04
3
05
BRCLR2
3
06
3
07
BRCLR3
3
08
3
09
BRCLR4
3
0A
3
0B
BRCLR5
3
0C
3
0D
BRCLR6
3
0E
3
0F
BRCLR7
3
INH
IMM
DIR
EXT
DD
IX+D
BRSET0
BRSET1
BRSET2
BRSET3
BRSET4
BRSET5
BRSET6
BRSET7
Bit-Manipulation
Freescale Semiconductor
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
Inherent
Immediate
Direct
Extended
DIR to DIR
IX+ to DIR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
10
2
11
2
12
2
13
2
14
2
15
2
16
2
17
2
18
2
19
2
1A
2
1B
2
1C
2
1D
2
1E
2
1F
2
BSET0
BCLR0
BSET1
BCLR1
BSET2
BCLR2
BSET3
BCLR3
BSET4
BCLR4
BSET5
BCLR5
BSET6
BCLR6
BSET7
BCLR7
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
20
2
21
2
22
2
23
2
24
2
25
2
26
2
27
2
28
2
29
2
2A
2
2B
2
2C
2
2D
2
2E
2
2F
2
Branch
BHCC
BHCS
BRN
BCC
BEQ
BMC
BMS
BRA
BLS
BCS
BNE
BPL
BMI
BHI
BIH
BIL
REL
IX
IX1
IX2
IMD
DIX+
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
30
2
31
3
32
3
33
2
34
2
35
2
36
2
37
2
38
2
39
2
3A
2
3B
3
3C
2
3D
2
3E
3
3F
2
Relative
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
IMM to DIR
DIR to IX+
CBEQ
LDHX
STHX
DBNZ
CPHX
COM
NEG
ROR
LSR
ASR
ROL
DEC
CLR
LSL
TST
INC
EXT
EXT
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
4
5
5
5
5
5
7
5
4
6
5
40
1
41
3
42
1
43
1
44
1
45
3
46
1
47
1
48
1
49
1
4A
1
4B
2
4C
1
4D
1
4E
3
4F
1
CBEQA
DBNZA
COMA
NEGA
RORA
ASRA
DECA
LSRA
LDHX
ROLA
CLRA
LSLA
INCA
TSTA
MOV
MUL
IMM
IMM
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
DD
Read-Modify-Write
Table 6-2 Opcode Map (Sheet 1 of 2)
1
4
5
1
1
3
1
1
1
1
1
4
1
1
5
1
50
1
51
3
52
1
53
1
54
1
55
2
56
1
57
1
58
1
59
1
5A
1
5B
2
5C
1
5D
1
5E
2
5F
1
CBEQX
DBNZX
COMX
NEGX
RORX
DECX
LSRX
LDHX
ASRX
ROLX
CLRX
LSLX
TSTX
INCX
MOV
DIV
SP1
SP2
IX+
IX1+
DIX+
IMM
INH
INH
INH
INH
DIR
INH
INH
INH
INH
INH
INH
INH
INH
INH
1
4
6
1
1
4
1
1
1
1
1
4
1
1
5
1
60
2
61
3
62
1
63
2
64
2
65
3
66
2
67
2
68
2
69
2
6A
2
6B
3
6C
2
6D
2
6E
3
6F
2
Stack Pointer, 8-Bit Offset
Stack Pointer, 16-Bit Offset
Indexed, No Offset with
Post Increment
Indexed, 1-Byte Offset with
Post Increment
CBEQ
CPHX
DBNZ
COM
NEG
ROR
MOV
NSA
LSR
ASR
ROL
DEC
CLR
LSL
TST
INC
MC9S08RC/RD/RE/RG
IX1+
IMM
IMD
INH
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
5
5
1
5
5
3
5
5
5
5
5
7
5
4
4
5
70
1
71
2
72
1
73
1
74
1
75
2
76
1
77
1
78
1
79
1
7A
1
7B
2
7C
1
7D
1
7E
2
7F
1
CBEQ
CPHX
DBNZ
COM
ROR
MOV
NEG
DAA
ASR
ROL
DEC
CLR
LSR
TST
LSL
INC
IX+D
INH
DIR
IX+
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
4
5
1
4
4
5
4
4
4
4
4
6
4
3
5
4
80
1
81
1
82
1
83
1
84
1
85
1
86
1
87
1
88
1
89
1
8A
1
8B
1
8C
1
8E
1
8F
1
BGND
PSHH
PULA
PSHA
PULX
PSHX
PULH
CLRH
STOP
WAIT
RTS
SWI
TAP
TPA
RTI
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
5+
2+
2+
Control
11
9
6
1
1
3
2
3
2
3
2
1
90
2
91
2
92
2
93
2
94
1
95
1
96
3
97
1
98
1
99
1
9A
1
9B
1
9C
1
9D
1
9E
9F
1
Page 2
STHX
BGE
NOP
BGT
TXS
TSX
CLC
SEC
RSP
TXA
BLE
TAX
BLT
SEI
CLI
REL
REL
REL
REL
EXT
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
3
3
3
3
2
2
5
1
1
1
1
1
1
1
1
SoC Guide — MC9S08RG60/D Rev 1.10
A0
2
A1
2
A2
2
A3
2
A4
2
A5
2
A6
2
A7
2
A8
2
A9
2
AA
2
AB
2
AD
2
AE
2
AF
2
CMP
EOR
ORA
SUB
SBC
CPX
AND
ADC
ADD
BSR
LDA
LDX
BIT
AIS
AIX
Number of Bytes
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
REL
IMM
IMM
2
2
2
2
2
2
2
2
2
2
2
2
5
2
2
Hexadecimal
Opcode in
B0
2
B1
2
B2
2
B3
2
B4
2
B5
2
B6
2
B7
2
B8
2
B9
2
BA
2
BB
2
BC
2
BD
2
BE
2
BF
2
CMP
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
LDA
JMP
JSR
LDX
STX
STA
BIT
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
5
3
3
C0
3
C1
3
C2
3
C3
3
C4
3
C5
3
C6
3
C7
3
C8
3
C9
3
CA
3
CB
3
CC
3
CD
3
CE
3
CF
3
F0
1
Register/Memory
CMP
AND
EOR
ADC
ORA
ADD
SUB
SBC
CPX
JMP
LDX
STX
SUB
LDA
STA
JSR
BIT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
IX
4
4
4
4
4
4
4
4
4
4
4
4
4
6
4
4
3
D0
3
D1
3
D2
3
D3
3
D4
3
D5
3
D6
3
D7
3
D8
3
D9
3
DA
3
DB
3
DC
3
DD
3
DE
3
DF
3
HCS08 Cycles
Instruction Mnemonic
Addressing Mode
CMP
EOR
ORA
SUB
SBC
CPX
AND
ADC
ADD
JMP
LDA
STA
JSR
LDX
STX
BIT
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
4
4
4
4
4
4
4
4
4
4
4
4
4
6
4
4
E0
2
E1
2
E2
2
E3
2
E4
2
E5
2
E6
2
E7
2
E8
2
E9
2
EA
2
EB
2
EC
2
ED
2
EE
2
EF
2
CMP
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
LDA
JMP
JSR
LDX
STX
STA
BIT
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
3
3
3
3
3
3
3
3
3
3
3
3
3
5
3
3
F0
1
F1
1
F2
1
F3
1
F4
1
F5
1
F6
1
F7
1
F8
1
F9
1
FA
1
FB
1
FC
1
FD
1
FE
1
FF
1
CMP
AND
EOR
ADC
ORA
ADD
SUB
SBC
CPX
JMP
LDX
STX
LDA
STA
JSR
BIT
91
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
3
3
3
3
3
3
3
2
3
3
3
3
3
5
3
2