mc9s08gt16a Freescale Semiconductor, Inc, mc9s08gt16a Datasheet - Page 190
mc9s08gt16a
Manufacturer Part Number
mc9s08gt16a
Description
Hcs08 Microcontrollers 8-bit Microcontroller Family
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08GT16A.pdf
(300 pages)
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Serial Peripheral Interface (S08SPIV3)
12.1.2
This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.
12.1.2.1
Figure 12-3
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave
select output.
The most common uses of the SPI system include connecting simple shift registers for adding input or
output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although
Figure 12-3
simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a
slave to the master MCU.
12.1.2.2
Figure 12-4
Data is written to the double-buffered transmitter (write to SPID) and gets transferred to the SPI shift
register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the
double-buffered receiver where it can be read (read from SPID). Pin multiplexing logic controls
connections between MCU pins and the SPI module.
190
7
6
Block Diagrams
shows a system where data is exchanged between two MCUs, many practical systems involve
is a block diagram of the SPI module. The central element of the SPI is the SPI shift register.
shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
SPI System Block Diagram
SPI Module Block Diagram
5
GENERATOR
SPI SHIFTER
MASTER
CLOCK
4
3
2
1
0
Figure 12-3. SPI System Connections
MC9S08GT16A/GT8A Data Sheet, Rev. 1
MOSI
MISO
SPSCK
SS
SPSCK
MOSI
MISO
SS
7
SLAVE
6
5
SPI SHIFTER
4
3
2
1
Freescale Semiconductor
0
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