mc9s08ac16 Freescale Semiconductor, Inc, mc9s08ac16 Datasheet - Page 169
mc9s08ac16
Manufacturer Part Number
mc9s08ac16
Description
Hcs08 Microcontrollers 8-bit Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08AC16.pdf
(338 pages)
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In Edge-Aligned PWM mode when (CLKSB:CLKSA not = 00),
writes to TPMxCnVH:L registers
In Center-Aligned PWM mode when (CLKSB:CLKSA not =
00), writes to TPMxCnVH:L registers
Center-Aligned PWM
When TPMxCnVH:L = TPMxMODH:L
When TPMxCnVH:L = (TPMxMODH:L - 1)
TPMxCnVH:L is changed from 0x0000 to a non-zero value
TPMxCnVH:L is changed from a non-zero value to 0x0000
Write to TPMxMODH:L registers in BDM mode
In BDM mode, a write to TPMxSC register
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
Table 10-1. TPMV2 and TPMV3 Porting Considerations (continued)
Action
Section 10.5.2, “TPM-Counter Registers
Section 10.5.5, “TPM Channel Value Registers
Section 10.6.2.1, “Input Capture
Section 10.6.2.4, “Center-Aligned PWM
Section 10.6.2.4, “Center-Aligned PWM
Section 10.6.2.4, “Center-Aligned PWM
Section 10.6.2.4, “Center-Aligned PWM
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5
MC9S08AC16 Series Data Sheet, Rev. 0
6
PRELIMINARY
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Update the TPMxCnVH:L
registers with the value of
their write buffer after both
bytes were written and when
the TPM counter changes
from (TPMxMODH:L - 1) to
(TPMxMODH:L).
Note: If the TPM counter is a
free-running counter, then
this update is made when the
TPM counter changes from
$FFFE to $FFFF.
Update the TPMxCnVH:L
registers with the value of
their write buffer after both
bytes are written and when
the TPM counter changes
from (TPMxMODH:L - 1) to
(TPMxMODH:L).
Note: If the TPM counter is a
free-running counter, then
this update is made when the
TPM counter changes from
$FFFE to $FFFF.
Produces 100% duty cycle.
Produces a near 100% duty
cycle.
Waits for the start of a new
PWM period to begin using
the new duty cycle setting.
Finishes the current PWM
period using the old duty
cycle setting.
Clears the write coherency
mechanism of TPMxMODH:L
registers.
Mode.”
Mode.”
Mode.” [SE110-TPM case 1]
Mode.” [SE110-TPM case 2]
Mode.” [SE110-TPM case 3 and 5]
(TPMxCNTH:TPMxCNTL).” [SE110-TPM case 7]
TPMV3
(TPMxCnVH:TPMxCnVL).”
Chapter 10 Timer/PWM (S08TPMV3)
Update after both bytes are
written and when the TPM
counter changes from
TPMxMODH:L to $0000.
Update after both bytes are
written and when the TPM
counter changes from
TPMxMODH:L to
(TPMxMODH:L - 1).
Produces 0% duty cycle.
Produces 0% duty cycle.
Changes the channel output at
the middle of the current PWM
period (when the count
reaches 0x0000).
Finishes the current PWM
period using the new duty cycle
setting.
Does not clear the write
coherency mechanism.
TPMV2
169
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