mc9s08lc60 Freescale Semiconductor, Inc, mc9s08lc60 Datasheet - Page 71
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mc9s08lc60
Manufacturer Part Number
mc9s08lc60
Description
Hcs08 Microcontrollers 8-bit Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08LC60.pdf
(360 pages)
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IRQMOD
IRQACK
IRQPE
IRQIE
Field
IRQF
4
3
2
1
0
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can
be used as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down
resistor is enabled depending on the state of the IRQMOD bit.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate a hardware
interrupt request.
0 Hardware interrupt requests from IRQF disabled (use polling).
1 Hardware interrupt requested whenever IRQF = 1.
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Table 5-3. IRQSC Field Descriptions (continued)
Section 5.5.2.2, “Edge and Level
Description
Sensitivity”
Chapter 5 Resets, Interrupts, and System Configuration
for more details.
71
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