cop8sec520m National Semiconductor Corporation, cop8sec520m Datasheet
cop8sec520m
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cop8sec520m Summary of contents
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... Nine multi-source vectored interrupts servicing — EERAM write complete — External interrupt — Idle Timer T0 — One Timer (with 2 Interrupts) — MICROWIRE/PLUS Serial Interface — Multi-Input Wake Up TRI-STATE ® registered trademark of National Semiconductor Corporation. MICROWIRE/PLUS ™ , COP8 ™ , MICROWIRE ™ and WATCHDOG iceMASTER ™ ...
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Block Diagram 1.0 Device Description 1.1 ARCHITECTURE The COP8 family is based on a modified Harvard architec- ture, which allows data tables to be accessed directly from program memory. This is very important with modern microcontroller-based applications, since program memory ...
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... The COP8 family offers a wide range of packages and does not waste pins 90.9% (or 40 pins in the 44-pin pack- age, these packages are not available on all COP8 devices) are devoted to useful I/O. Top View Order Number COP8SEC520M or COP8SER720M See NS Package Number M20B FIGURE 2. Connection Diagrams 3 DS100973-43 ...
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Connection Diagrams (Continued) Pinouts for 16-, and 20-Pin Packages Port Type L0 I/O L1 I/O L2 I/O L3 I/O L4 I/O L5 I/O L6 I/O L7 I/O G0 I/O G1 I/O G2 I/O G3 I/O G4 I/O G5 I/O G6 ...
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Electrical Characteristics Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin −0. Total Current into V ...
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DC Electrical Characteristics −40˚C T +85˚C unless otherwise specified. A Parameter Output Current Levels Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink Current per Pin Maximum Input Current without Latchup (Note 7) RAM Retention ...
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AC Electrical Characteristics −40˚C T +85˚C unless otherwise specified. A Parameter Instruction Cycle Time ( Crystal/Resonator R/C Oscillator Frequency Variation (Note 9), (Note 10) CKI Clock Duty Cycle (Note 9) Rise Time (Note 9) Fall Time (Note 9) ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin Total Current into V Pin CC (Source) Total Current out ...
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AC Electrical Characteristics −40˚C T +135˚C unless otherwise specified. A Parameter Instruction Cycle Time ( Crystal/Resonator, External R/C Oscillator (Internal) Frequency Variation (Note 22), (Note 21) CKI Clock Duty Cycle (Note 22) Rise Time (Note 22) Fall Time ...
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Pin Descriptions The device I/O structure enables designers to reconfigure the microcontroller’s I/O functions with a single instruction. Each individual I/O pin can be independently configured as output pin low, output high, input with high impedance or in- put ...
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Pin Descriptions (Continued) FIGURE 6. I/O Port Configurations — Output Mode FIGURE 7. I/O Port Configurations — Input Mode 5.0 Functional Description The architecture of the devices is a modified Harvard archi- tecture. With the Harvard architecture, the program ...
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Functional Description Caution: In order to prevent the unexpected setting of the ILRW of the E2CFG Register and the corresponding interrupt, the use of the X Register and direct addressing are recommanded for EERAM ac- cess further ...
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Functional Description not changed by these instructions. Consequently, the stack (used with subroutine linkage and interrupts) is always lo- cated in the base segment. The stack pointer will be initial- ized to point at data memory location 006F as ...
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Functional Description DS100973-50 5.9.1 Crystal Oscillator CKI and CKO can be connected to make a closed loop crys- tal (or resonator) controlled oscillator. Table 1 shows the component values required for various standard crystal values. TABLE 1. Crystal Oscillator ...
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Functional Description 5.10 CONTROL REGISTERS CNTRL Register (Address X'00EE) T1C3 T1C2 T1C1 T1C0 MSEL IEDG Bit 7 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control ...
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Timers (Continued) FIGURE 11. Functional Block Diagram for Idle Timer T0 6.2 TIMER T1 The device has a powerful timer/counter block. The timer consists of a 16-bit timer, T1, and two supporting 16-bit autoreload/capture registers, R1A and R1B. The ...
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Timers (Continued) 6.2.2 Mode 2. External Event Counter Mode This mode is quite similar to the processor independent PWM mode previously described. The main difference is that the timer, T1, is clocked by the input signal from the T1A ...
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Timers (Continued) 6.3 TIMER CONTROL FLAGS The Timer T1 control bits and their functions are summarized below. T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control T1C0 Timer Start/Stop control in Modes 1 and 2 (Pro- ...
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Power Saving Features Today, the proliferation of battery-operated based applica- tions has placed new demands on designers to drive power consumption down. Battery-operated systems are not the only type of applications demanding low power. The power budget constraints are ...
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Power Saving Features 7.2 IDLE MODE The device is placed in the IDLE mode by writing the IDLE flag (G6 data bit). In this mode, all activity, except the associated on-board oscillator circuitry, the WATCHDOG logic, ...
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Power Saving Features 7.3 MULTI-INPUT WAKEUP The Multi-Input Wakeup feature is used to return (wakeup) the device from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be used to generate edge selectable ...
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Power Saving Features 8.0 Interrupts 8.1 INTRODUCTION Each device supports eight vectored interrupts. Interrupt sources include Timer 0, Timer 1, EERAM Write Complete, Port L Wakeup, Software Trap, MICROWIRE/PLUS, and Ex- ternal Input. All interrupts force a branch to ...
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Interrupts (Continued) 8.2 MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The ...
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Interrupts (Continued) ample, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap in- terrupt occurs and the VIS ...
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Interrupts (Continued) 8.3.1 VIS Execution When the VIS instruction is executed it activates the arbitra- tion logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has ...
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Interrupts (Continued) www.national.com DS100973-30 FIGURE 20. VIS Flowchart 26 ...
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Interrupts (Continued) Programming Example: External Interrupt PSW =00EF CNTRL =00EE RBIT 0,PORTGC RBIT 0,PORTGD SBIT IEDG, CNTRL SBIT EXEN, PSW SBIT GIE, PSW WAIT: JP WAIT . . . .=0FF VIS . . . .=01FA .ADDRW SERVICE . . ...
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Interrupts (Continued) 8.4 NON-MASKABLE INTERRUPT 8.4.1 Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory- mapped and cannot be accessed directly by the software. The pending flag ...
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WATCHDOG/Clock Monitor Each device contains a user selectable WATCHDOG and clock monitor. The following section is applicable only if WATCHDOG feature has been selected by mask option. The WATCHDOG is designed to detect the user program getting stuck in ...
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WATCHDOG/Clock Monitor Key Window Data Data Match Match Don’t Care Mismatch Mismatch Don’t Care Don’t Care Don’t Care 9.3 WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted: • Both ...
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MICROWIRE/PLUS MICROWIRE/PLUS is a serial SPI compatible synchronous communications interface. The MICROWIRE/PLUS capabil- ity enables the device to interface with MICROWIRE/PLUS or SPI peripherals (i.e. A/D converters, display drivers, EE- PROMs etc.) and with other microcontrollers which support the ...
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MICROWIRE/PLUS 10.1.2 MICROWIRE/PLUS Slave Mode Operation In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G ...
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MICROWIRE/PLUS (Continued) FIGURE 24. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High FIGURE 25. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High DS100973-35 DS100973-31 33 www.national.com ...
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Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents S/ADD REG 0000 to 006F On-Chip RAM bytes (112 bytes) 0070 to 007F Unused RAM Address Space (Reads As ...
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Instruction Set 12.1 INTRODUCTION This section defines the instruction set of the COPSAx7 Family members. It contains information about the instruc- tion set features, addressing modes and types. 12.2 INSTRUCTION FEATURES The strength of the instruction set is based ...
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Instruction Set (Continued) Example: Load Accumulator Immediate Reg/Data Contents Memory Before Accumulator XX Hex Immediate Short. This is a special case of an immediate in- struction. In the “Load B immediate” instruction, the 4-bit im- ...
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Instruction Set (Continued) Jump Indirect. In this 1-byte instruction, the lower byte of the jump address is obtained from a table stored in program memory, with the Accumulator serving as the low order byte of a pointer into program ...
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Instruction Set (Continued) 12.4.9 No-Operation Instruction The no-operation instruction does nothing, except to occupy space in the program memory and time in execution. No-Operation (NOP) Note: The VIS is a special case of the Indirect Transfer of Control addressing ...
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Instruction Set (Continued) ± LoaD A with Memory [B] ± LoaD A with Memory [X] ± ],Imm LoaD Memory [B] Immed. CLR A CLeaR A INC A INCrement A ...
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Instruction Set (Continued) 12.7 INSTRUCTION EXECUTION TIME Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be ...
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Instruction Set (Continued) Nibble Lower 41 www.national.com ...
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Mask Options For COP8SEC5 The mask options for this device are described below. These options are programmed at the same time as the ROM pat- tern and therefore must be submitted with the ROM pattern. OPTION 1: Clock configuration ...
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Development Support • COP8-NSDEV: Very low cost Software Development Package for Windows. An integrated development envi- ronment for COP8, including WCOP8 IDE, COP8C (lim- ited version), COP8-NSASM, COP8-MLSIM. • COP8C: Moderately priced C Cross-Compiler and Code Development System from ...
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Development Support 14.3 TOOLS ORDERING NUMBERS FOR THE COP8SEx FAMILY DEVICES Vendor Tools Order Number National COP8-NSEVAL COP8-NSEVAL COP8-NSASM COP8-NSASM COP8-MLSIM COP8-MLSIM COP8-NSDEV COP8-NSDEV COP8-EPU Not available for this device COP8-DM Contact metaLink Development COP8SER7 Devices IM-COP8 Contact MetaLink ...
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Development Support 14.4 WHERE TO GET TOOLS Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors. Vendor Home Office Aisys U.S.A.: Santa Clara, CA 1-408-327-8820 fax: 1-408-327-8830 Byte ...
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... Physical Dimensions inches (millimeters) unless otherwise noted www.national.com Molded SO Wide Body Package (WM) Order Number COP8SEC516M, NS Package Number M16B Molded SO Wide Body Package (WM) Order Number COP8SEC520M, NS Package Number M20B 46 ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...