cop8scr9lva8 National Semiconductor Corporation, cop8scr9lva8 Datasheet - Page 58

• Manufacturer Part Number: cop8scr9lva8
• Description: 8-bit Cmos Flash Based Microcontroller With 32k Memory, Virtual Eeprom And Brownoutff
• Manufacturer: National Semiconductor Corporation

www.national.com
16.0 WATCHDOG/Clock Monitor
trigger threshold. After this delay, the device will stop forcing
the WDOUT output low. The WATCHDOG service window
will restart when the WDOUT pin goes high.
A WATCHDOG service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
on reset, but if it powers up low then the WATCHDOG will
time out and WDOUT will go high.
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
16.3 WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:
• Both the WATCHDOG and CLOCK MONITOR detector
• Following RESET, the WATCHDOG and CLOCK MONI-
• The WATCHDOG service window and CLOCK MONI-
• The initial WATCHDOG service must match the key data
• Subsequent WATCHDOG services must match all three
• The correct key data value cannot be read from the
• The WATCHDOG detector circuit is inhibited during both
• The CLOCK MONITOR detector circuit is active during
• The WATCHDOG service window will be set to its se-
• The IDLE timer T0 is not initialized with external RESET.
(Continued)
circuits are inhibited during RESET.
TOR are both enabled, with the WATCHDOG having the
maximum service window selected.
TOR enable/disable option can only be changed once,
during the initial WATCHDOG service following RESET.
value in the WATCHDOG Service register WDSVR in
order to avoid a WATCHDOG error.
data fields in WDSVR in order to avoid WATCHDOG
errors.
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s.
the HALT and IDLE modes.
both the HALT and IDLE modes. Consequently, the de-
vice inadvertently entering the HALT mode will be de-
tected as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by
the program). Likewise, a device with WATCHDOG en-
abled in the Option but with the WATCHDOG output not
connected to RESET, will draw excessive HALT current if
placed in the HALT mode. The clock Monitor will pull the
WATCHDOG output low and sink current through the
on-chip pull-up resistor.
lected value from WDSVR following HALT. Consequently,
the WATCHDOG should not be serviced for at least 2048
Idle Timer clocks following HALT, but must be serviced
within the selected window to avoid a WATCHDOG error.
Don’t Care
Don’t Care
Mismatch
Match
Data
Key
Don’t Care
Don’t Care
Mismatch
Window
Match
Data
TABLE 22. WATCHDOG Service Actions
Don’t Care
Don’t Care
Mismatch
Monitor
Clock
Match
58
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
until the clock frequency has reached the minimum specified
value, after which the G1 output will go high following 16–32
clock cycles. The Clock Monitor generates a continual Clock
Monitor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the Clock
Monitor is as follows:
• The user can sync in to the IDLE counter cycle with an
• A hardware WATCHDOG service occurs just as the de-
• Following RESET, the initial WATCHDOG service (where
• When using any of the ISP functions in Boot ROM, the
16.4 DETECTION OF ILLEGAL CONDITIONS
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
Reading of unprogrammed ROM gets zeros. The opcode for
software interrupt is 00. If the program fetches instructions
from unprogrammed ROM, this will force a software inter-
rupt, thus signaling that an illegal condition has occurred.
The subroutine stack grows down for each call (jump to
subroutine), interrupt, or PUSH, and grows up for each
return or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more re-
turns than calls, the stack pointer will point to addresses 070
and 071 Hex (which are undefined RAM). Undefined RAM
from addresses 070 to 07F (Segment 0), and all other seg-
ments (i.e., Segments 4... etc.) is read as all 1’s, which in
1/t
1/t
IDLE counter (T0) interrupt or by monitoring the T0PND
flag. The T0PND flag is set whenever the selected bit of
the IDLE counter toggles (every 4, 8, 16, 32 or 64k Idle
Timer clocks). The user is responsible for resetting the
T0PND flag.
vice
WATCHDOG should not be serviced for at least 2048 Idle
Timer clocks following IDLE, but must be serviced within
the selected window to avoid a WATCHDOG error.
the service window and the CLOCK MONITOR enable/
disable must be selected) may be programmed any-
where within the maximum service window (65,536 in-
struction cycles) initialized by RESET. Note that this initial
WATCHDOG service may be programmed within the ini-
tial
WATCHDOG error.
ISP routines will service the WATCHDOG within the se-
lected upper window. Upon return to flash memory, the
WATCHDOG is serviced, the lower window is enabled,
and the user can service the WATCHDOG anytime fol-
lowing exit from Boot ROM, but must service it within the
selected upper window to avoid a WATCHDOG error.
C
C
>
<
2048
5 kHz — No clock rejection.
10 Hz — Guaranteed clock rejection.
exits
Action
instruction
the
IDLE
cycles
mode.
without
Consequently,
causing
the
a