cop87l84cf ETC-unknow, cop87l84cf Datasheet - Page 12

• Manufacturer Part Number: cop87l84cf
• Description: 8-bit Cmos Microcontrollers With Memory
• Manufacturer: ETC-unknow

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Oscillator Circuits
Note: 3k
Control Registers
CNTRL Register (Address X'00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
PSW Register (Address X'00EF)
The PSW register contains the following select bits:
Bit 7
Bit 7
T1C3
TABLE 1. Crystal Oscillator Configuration, T
(k )
HC
(k )
R1
T1C3
T1C2
T1C1
T1C0
MSEL
IEDG
SL1 & SL0
HC
C
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
T1ENA
EXPND
BUSY
EXEN
GIE
3.3
5.6
6.8
0
0
0
R
TABLE 2. R/C Oscillator Configuration, T
50 pF
C
T1C2
R
(M )
R2
(pF)
100
100
1
1
1
T1PNDA
82
C
C
200k
Half Carry Flag
Carry Flag
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
External interrupt pending
MICROWIRE/PLUS busy shifting flag
Enable external interrupt
Global interrupt enable (enables interrupts)
200 pF
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
T1C1
(pF)
200
C1
30
30
CKI Freq
2.2 to 2.7
1.1 to 1.3
0.9 to 1.1
(MHz)
T1ENA
T1C0
100–150
30–36
30–36
(pF)
C2
EXPND
(Continued)
8.8 to 10.8
MSEL
3.7 to 4.6
7.4 to 9.0
Cycle
Instr.
(µs)
(MHz)
0.455
Freq
CKI
BUSY
10
IEDG
4
Conditions
Conditions
A
EXEN
V
V
V
V
V
V
SL1
CC
CC
CC
A
= 25˚C
CC
CC
CC
= 25˚C
= 5V
= 5V
= 5V
= 5V
= 5V
= 5V
Bit 0
GIE
SL0
Bit 0
12
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
The ICNTRL register contains the following bits:
T2CNTRL Register (Address X'00C6)
The T2CNTRL control register contains the following bits:
Timers
The device contains a very versatile set of timers (T0, T1,
T2). All timers and associated autoreload/capture registers
power up containing random data.
Figure 7 shows a block diagram for the timers.
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed rate
of the instruction cycle clock, t
write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
Reserved
Bit 7
T2C3
Bit 7
Reserved This bit is reserved and must be zero
LPEN
T0PND
T0EN
µWPND
µWEN
T1PNDB
T1ENB
T2C3
T2C2
T2C1
T2C0
T2PNDA
T2ENA
T2PNDB
T2ENB
Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
T2C2
LPEN
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
Timer T0 Interrupt pending
Timer T0 Interrupt Enable (Bit 12 toggle)
MICROWIRE/PLUS interrupt pending
Enable MICROWIRE/PLUS interrupt
Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
Timer T1 Interrupt Enable for T1B Input cap-
ture edge
Timer T2 mode control bit
Timer T2 mode control bit
Timer T2 mode control bit
Timer
modes 1 and 2, T2 Underflow Interrupt Pend-
ing Flag in timer mode 3
Timer T2 Interrupt Pending Flag (Autoreload
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
Timer T2 Interrupt Pending Flag for T2B cap-
ture edge
Timer T2 Interrupt Enable for Timer Underflow
or T2B Input capture edge
T2C1
T0PND
T2C0
T2
T0EN
T2PNDA
Start/Stop
µWPND
c
. The user cannot read or
T2ENA
µWEN
control
T2PNDB
T1PNDB
in
T2ENB
T1ENB
timer
Bit 0
Bit 0