sx20ac Parallax, Inc., sx20ac Datasheet - Page 39

• Manufacturer Part Number: sx20ac
• Description: Configurable Communications Controllers With Ee/flash Program Memory, In-system Programming Capability And On-chip Debug
• Manufacturer: Parallax, Inc.

Parallax SX20AC/SX28AC
16.1.
Some
mnemonics that are special cases of existing instructions
or alternative mnemonics for standard ones. For example,
an assembler might support the mnemonic “CLC” (clear
Note 1: The JMP W and JMP PC+W instructions take 4 cycles in the Slow clocking mode, or 3 cycles in the Turbo clocking mode.
Note 2: The SC instruction takes 1 cycle if the tested condition is false or 2 cycles if the tested condition is true.
Note 3: The assembler converts the SKIP instruction into a SNB or SB instruction that tests the least significant bit of the program
counter, choosing SNB or SB so that the tested condition is always true. The instruction takes 4 cycles in the Slow clocking mode
or 2 cycles in theTurbo clocking mode.
© Parallax Inc.
CLC
CLZ
JMP W
JMP PC+W
MODE imm4
NOT W
SC
SKIP
assemblers
Equivalent Assembler Mnemonics
Syntax
support
Clear Carry bit
Clear Zero bit
Jump Indirect W
Jump Indirect W Relative
Move Immediate to MODE
Register
Complement of W
Skip if Carry bit set
Skip Next Instruction
Table 16-7: SX Equivalent Assembler Mnemonics
additional
Description
instruction
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carry), which is interpreted the same as the instruction
“clrb $03.0” (clear bit 0 in the STATUS register). Some
of the commonly supported equivalent assembler
mnemonics are described in Table 16-7.
SNB $02.0 or SB $02.0
XOR W,#$FF
Equivalent
CLRB $03.0
MOV $02,W
CLRB $03.2
ADD $02,W
MOV M,#lit
SB $03.0
4 or 3 (see Note 1)
4 or 3 (see Note 1)
1 or 2 (see Note 2)
4 or 2 (see Note 3)
Cycles
Rev 1.6 11/20/2006
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