m37702s1afp Mitsumi Electronics, Corp., m37702s1afp Datasheet - Page 11

• Manufacturer Part Number: m37702s1afp
• Description: Single-chip 16-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Instruction code read will be described first.
The CPU obtains instruction codes from the instruction queue
buffer and executes them. The CPU notifies the bus interface unit
that it is requesting an instruction code during an instruction code
request cycle. If the requested instruction code is not yet stored in
the instruction queue buffer, the bus interface unit halts the CPU
until it can store more instructions than requested in the instruction
queue buffer.
Even if there is no instruction code request from the CPU, the bus
interface unit reads instruction codes from memory and stores
them in the instruction queue buffer when the instruction queue
buffer is empty or when only one instruction code is stored and the
bus is idle on the next cycle.
This is referred to as instruction pre-fetching.
Normally, when reading an instruction code from memory, if the
accessed address is even the next odd address is read together
with the instruction code and stored in the instruction queue buffer.
However, in memory expansion mode or microprocessor mode, if
the bus width switching pin BYTE is “H”, external data bus width is
8 bits and the address to be read is in external memory area is
odd, only one byte is read and stored in the instruction queue
buffer. Therefore, waveform (1) or (3) in Figure 5 is used for in-
struction code read.
Data read and write are described below.
The CPU notifies the bus interface unit when performing data read
or write. At this time, the bus interface unit halts the CPU if the bus
interface unit is already using the bus or if there is a request with
higher priority. When data read or write is enabled, the bus inter-
face unit uses one of the waveforms from (1) to (6) in Figure 5 to
perform the operation.
During data read, the CPU waits until the entire data is stored in
the data buffer. The bus interface unit sends the address received
from the CPU to the address bus. Then it reads the memory when
_
the E signal is “L” and stores the result in the data buffer.
During data write, the CPU writes the data in the data buffer and
the bus interface unit writes it to memory. Therefore, the CPU can
proceed to the next step without waiting for write to complete. The
bus interface unit sends the address received from the CPU to the
_
address bus. Then when the E signal is “L”, the bus interface unit
sends the data in the data buffer to the data bus and writes it to
memory.
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