lmp8602mmx National Semiconductor Corporation, lmp8602mmx Datasheet - Page 18

• Manufacturer Part Number: lmp8602mmx
• Description: 60v Common Mode, Fixed Gain, Bidirectional Precision Current Sensing Amplifier
• Manufacturer: National Semiconductor Corporation

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BIDIRECTIONAL CURRENT SENSING
The signal on the A1 and OUT pins is ground-referenced
when the OFFSET pin is connected to ground. This means
that the output signal can only represent positive values of the
current through the shunt resistor, so only currents flowing in
one direction can be measured. When the offset pin is tied to
the positive supply rail, the signal on the A1 and OUT pins is
referenced to a mid-rail voltage which allows bidirectional
current sensing. When the offset pin is connected to a voltage
source, the output signal will be level shifted to that voltage
divided by two. In principle, the output signal can be shifted
to any voltage between 0 and V
voltage from a low impedance source (Note 16) to the OFF-
SET pin.
With the offset pin connected to the supply pin (V
ation of the amplifier will be fully bidirectional and symmetrical
around 0V differential at the input pins. The signal at the out-
put will follow this voltage difference multiplied by the gain and
at an offset voltage at the output of half V
Example:
With 5V supply and a gain of 50x for the LMP8602, a differ-
ential input signal of +10 mV will result in 3.0V at the output
pin. similarly -10 mV at the input will result in 2.0V at the output
pin.
With 5V supply and a gain of 100x for the LMP8603, a differ-
ential input signal of +10 mV will result in 3.5V at the output
pin. similarly -10 mV at the input will result in 1.5V at the output
pin.
Note 16: The OFFSET pin has to be driven from a very low-impedance
source (<10Ω). This is because the OFFSET pin internally connects directly
to the resistive feedback networks of the two gain stages. When the OFFSET
pin is driven from a relatively large impedance (e.g. a resistive divider
between the supply rails) accuracy will decrease.
POWER SUPPLY DECOUPLING
In order to decouple the LMP8602/LMP8603 from AC noise
on the power supply, it is recommended to use a 0.1 µF by-
pass capacitor between the V
should be placed as close as possible to the supply pins. In
some cases an additional 10 µF bypass capacitor may further
reduce the supply noise.
LAYOUT CONSIDERATIONS
The two input signals of the LMP8602/LMP8603 are differen-
tial signals and should be handled as a differential pair. For
optimum performance these signals should be closely togeth-
er and of equal length. Keep all impedances in both traces
equal and do not allow any other signal or ground in between
the traces of this signals.
The connection between the preamplifier and the output
buffer amplifier is a high impedance signal due to the 100
kΩ series resistor at the output of the preamplifier. Keep the
traces at this point as short as possible and away from inter-
fering signals.
The LMP8602/LMP8603 is available in a 8–Pin SOIC pack-
age and in a 8–Pin MSOP package. For the MSOP package,
the bare board spacing at the solder pads of the package will
be too small for reliable use at higher voltages (V
this situation it is strongly advised to add a conformal coating
on the PCB assembled with the LMP8602/LMP8603 in MSOP
package.
DRIVING SWITCHED CAPACITIVE LOADS
Some ADCs load their signal source with a sample and hold
capacitor. The capacitor may be discharged prior to being
connected to the signal source. If the LMP8602/LMP8603 is
S
and GND pins. This capacitor
S
/2 by applying twice that
S
.
CM
S
) the oper-
> 25V) In
18
driving such ADCs the sudden current that should be deliv-
ered when the sampling occurs may disturb the output signal.
This effect was simulated with the circuit shown in Figure 5
where the output is to a capacitor that is driven by a rail to rail
square wave.
This circuit simulates the switched connection of a discharged
capacitor to the LMP8602/LMP8603 output. The resulting
V
and Figure 7.
These figures can be used to estimate the disturbance that
will be caused when driving a switched capacitive load. To
minimize the error signal introduced by the sampling that oc-
curs on the ADC input, an additional RC filter can be placed
OUT
FIGURE 6. Capacitive Load Response at 3.3V
FIGURE 7. Capacitive Load Response at 5.0V
FIGURE 5. Driving Switched Capacitive Load
disturbance
signals
are
shown
in
30083430
30083431
Figure
30083460
6