km416s4030c Samsung Semiconductor, Inc., km416s4030c Datasheet - Page 2

• Manufacturer Part Number: km416s4030c
• Description: 1m X 16bit X 4 Banks Synchronous Dram
• Manufacturer: Samsung Semiconductor, Inc.

KM416S4030C
1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
FUNCTIONAL BLOCK DIAGRAM
clock
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
-. CAS latency (2 & 3)
ADD
CLK
LCKE
CLK
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
Latency & Burst Length
GENERAL DESCRIPTION
rate Dynamic RAM organized as 4 x 1,048,576 words by 16
bits, fabricated with SAMSUNG s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Programming Register
WE
The KM416S4030C is 67,108,864 bits synchronous high data
Data Input Register
KM416S4030CT-G/F7
KM416S4030CT-G/F8
KM416S4030CT-G/FH
KM416S4030CT-G/FL
KM416S4030CT-G/F10
Column Decoder
1M x 16
1M x 16
1M x 16
1M x 16
L(U)DQM
Part No.
LWCBR
*
Samsung Electronics reserves the right to
change products or specification without
notice.
Max Freq.
143MHz
125MHz
100MHz
100MHz
100MHz
Preliminary
CMOS SDRAM
REV. 2 June '98
LDQM
Interface Package
LVTTL
LWE
LDQM
DQi
TSOP(II)
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