ata5780 ATMEL Corporation, ata5780 Datasheet - Page 15

• Manufacturer Part Number: ata5780
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

9207BS–RKE–01/11
The internal states of the demodulator are reset by disabling the complete Rx
DSP(RDCR.RDEN=0), by activati ng the p o w e r re d u c t i on f o r t he c h an n e l fil te r
(RDPR.PRFLT=1), or by activating only the power reduction for the reception path A/B
(RDPR.PRPTA/B=1).
In the demodulator block the signal is processed in two identical paths A and B operated in
parallel. Each single path consists of the following:
FSK Demodulation
The demodulator is based on a digital PLL. The demodulating process starts with carrier fre-
quency detection of the useful signal, which is the (assumed) dominant frequency within the
spectrum in the channel filter. The demodulator is centered using the measured frequency off-
set approaching the desired frequency. The time constant of the regulation loop is changed
stepwise for this purpose. The final setting depends on the deviation and data rate of the sig-
nal to be received and is stored separately for path A and B (in the value DMCRx.DMPGx).
The effective bandwidth for the demodulation process is therefore smaller, resulting in a
higher CNR.
The duration of the carrier frequency detection and centering depends on the selected loop
gain in DMCRx.DMPGx. The loop gain must be set to achieve an appropriate output signal for
the expected deviation and data rate.
Please note that for a certain setting the supported frequency deviation range and data rate is
limited. This block provides the frequency offset value RXFOx of the received signal.
The loop coefficients of path A and path B is changed during the first stage of reception in
order to lock to the signal. The final value of A depends on DMPGx and B is 1/2048.
ASK Demodulation
The ASK demodulation is achieved by calculating the magnitude of the complex (I-Q) base-
band signal in a logarithmic scale. Before the signal enters the filters it is limited to achieve the
amplitude range from detected peak level down to 23dB. The parameters of the peak detec-
tion are scaled by the selected data rate range in each path.
Post-detection Filtering (Data Filter)
Further filtering and decimation is done for signal paths A and B by a 2-stage filter followed by
a data slicer. The first stage contains 2
down-sampling. The down-sampling ratio is 2
by a moving average filter whose length is derived from the DMDRx.DMAx value.
• Demodulating part
• Post-detection filtering
• Data slicer
• Clock recovery
• Symbol check
Atmel ATA5780 [Preliminary]
nd
DMDRx.DMDNx
order CIC architecture with programmable
. In addition, the signal is processed
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