ata5277-pcq ATMEL Corporation, ata5277-pcq Datasheet - Page 14

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ata5277-pcq

Manufacturer Part Number
ata5277-pcq
Description
Stand-alone Antenna Driver
Manufacturer
ATMEL Corporation
Datasheet
Switch Inputs
CLKO Output Pin
14
ATA5277 [Preliminary]
Table 10. Diagnostic Bits
The switch inputs SW1 and SW2 can be used to connect switches, e.g., the door handle
contactors. These inputs are equipped with pull-ups, capable of driving currents up to
20 mA per pin. The pull-up voltage can be selected with the VSW input pin, which has to
be connected either to V
The state of the switches is determined by the voltage level at the corresponding pin.
This information can be read out via the DIO-line during the status command 3. If the IC
is in the standby mode, it wakes up if an input is pulled to ground. After a debounce time
the IC generates a low signal at the DIO-line (wake-up). This signal can be used to wake
up and request a microcontroller to read the switches with a setup cycle. Once the IC
has woken up or during normal operation mode, a low state at a switch input (i.e., the
switch is triggered) is stored until the status command 3 has been read out or ALYA
enters standby mode. This enables the microcontroller to determine which of the two
switch inputs was triggered, independant of the time it needs for processing status com-
mand 3.
To prevent high standby currents caused by a hanging door switch or a short-circuited
line, the pull-ups can be disabled individually by setting the DIS_SW1 and the DIS_SW2
bits in the command register 2.
The clock output pin CLKO on the ATA5277 can be used to supply an onboard micro-
controller with a clock signal (either 8 or 4 MHz). Due to this frequency and the 5-V
output stage, this signal is not suited to supply any device beyond the PCB boundaries.
This clock signal is directly derived from the clock source connected to the OSCI/OSCO
pins of the ATA5277 and is available as long as ATA5277 is not in standby mode. The
frequency can be selected with the PS_CLK bit of control command 2, which is '0' for full
clock rate (typical 8 MHz) or '1' for the half clock rate (4 MHz).
DIAG0
0
1
0
1
0
1
0
1
DIAG1
0
0
1
1
0
0
1
1
DD
(5 V) for 5 V operation or to V
DIAG2
0
0
0
0
1
1
1
1
Fault Type
No fault detected
Open load or QSC transistor SC to GND
Overtemperature
Antenna driver SC to GND
Antenna driver SC to V
QSC transistor SC to V
Not defined
Not defined
BATT
for 12 V operation.
BATT
BATT
4669B–RKE–10/03

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