lf3311 LOGIC Devices Incorporated, lf3311 Datasheet - Page 5

• Manufacturer Part Number: lf3311
• Description: Horizontal / Vertical Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
I/D Register Data
Path Control
Data Reversal
LOGIC Devices Incorporated
When the filter is configured for an odd number of taps, the data which will appear at the output of the last
I/D Register in the forward data path on the next clock cycle is fed into the first I/D Register in the reverse
data path. Bit 5 in Configuration Register 1 configures the filter for an even or odd number of taps.
When interleaved data is fed through the device and an even tap filter is desired, the filter should be
configured for an even number of taps (Bit 5 of CR1 set to “0”) and the I/D Register length should match
the number of data sets interleaved together. When interleaved data is to be fed through the device and
an odd tap filter is desired, the filter should be set to Odd-Tap Interleave Mode. Bit 0 of Configuration
Register 1 configures the filter for Odd-Tap Interleave Mode. When the filter is configured for Odd-Tap
Interleave Mode, data from the next to last I/D Register in the forward data path is fed into the first I/D
Register in the reverse data path.
When the filter is configured for an odd number of taps (interleaved or non-interleaved modes), the filter is
structured such that the center data value is aligned simultaneously at the A and B inputs of the last ALU in
the forward data path. In order to achieve the correct result, the user must divide the coefficient by two.
Data reversal circuitry is placed after the multiplexer which routes data from the forward data path to the
reverse data path (see Figure 6). When decimating, the data stream must be reversed in order for data to be
properly aligned at the inputs of the ALUs. When data reversal is enabled, the circuitry uses a pair of LIFOs
to reverse the order of the data sent to the reverse data path. When TXFR goes LOW, the LIFO sending
data to the reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO
receiving data from the forward data path becomes the LIFO sending data to the reverse data path. The
device must see a HIGH to LOW transition of TXFR in order to switch LIFOs. If decimating by N, TXFR
should go low once every N clock cycles. When data reversal is disabled, the circuitry functions like an
I/D Register. When feeding interleaved data through the filter, data reversal should be disabled. Bit 6 of
Configuration Register 1 enables or disables data reversal.
Functional Description
The multiplexer in the middle of the I/D Register data path controls how data is fed to the reverse data path.
The forward data path contains the I/D Registers in which data flows from left to right in the block diagram in
Figure 1. The reverse data path contains the I/D Registers in which data flows from right to left. When the
filter is configured for an even number of taps, data from the last I/D Register in the forward data path is fed
into the first I/D Register in the reverse data path (see Figure 5).
Figure 5. I/D Register Data Paths
EVEN-TAP MODE
A
ALU
B
A
ALU
B
COEF 7
COEF 6
5
A
ODD-TAP MODE
ALU
B
Horizontal / Vertical Digital Image Filter
A
ALU
B
Delay Stage N 1
Delay Stage N
COEF 7
COEF 6
2
Improved Performance
ODD-TAP INTERLEAVE MODE
Video Imaging Products
A
ALU
B
A
ALU
9/19/05 LDS.3311-C
B
LF3311
COEF 7
COEF 6
2