lf3330 LOGIC Devices Incorporated, lf3330 Datasheet - Page 3

• Manufacturer Part Number: lf3330
• Description: Vertical Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
Power
V
+3.3 V power supply. All pins must
be connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
Inputs
DIN
DIN
input port. Data is latched on the
rising edge of CLK.
VB
VB
input port used only when imple-
menting Odd and Even Field Filtering
(see Functional Description section for
a full discussion). Data is latched on
the rising edge of CLK.
CF
CF
coefficient banks and configuration/
control registers. Data present on
CF
face
LD is LOW (see the LF Interface
tion for a full discussion).
CA
CA
in the coefficient banks is fed to the
multipliers. CA
Coefficient Address Register on the
rising edge of CLK when CEN is
LOW.
Outputs
DOUT
DOUT
output port.
CC
11-0
11-0
11-0
11-0
11-0
7-0
7-0
TM
11-0
11-0
and GND
— Coefficient Address
determines which row of data
— Coefficient Input
on the rising edge of CLK when
15-0
15-0
is used to load data into the
is latched into the LF Inter-
— Field Filtering Data Input
is the 12-bit registered data
— Data Input
is the 12-bit registered data
— Data Output
is the 16-bit registered data
7-0
is latched into the
TM
sec-
COUT
COUT
port. COUT
be connected to DIN
LF3330.
Controls
LD — Coefficient Load
When LD is LOW, data on CF
latched into the LF Interface
rising edge of CLK. When LD is
HIGH, data can not be latched into the
LF Interface
Interface
LOW transition of LD is required in
order for the input circuitry to func-
tion properly. Therefore, LD must
be set HIGH immediately after power
up to ensure proper operation of the
input circuitry (see the LF Interface
section for a full discussion).
PAUSE — LF Interface
SLCT
F
T
00000
00001
00010
01110
01111
10000
IGURE
ABLE
·
·
·
(Sign)
11-0
11-0
4-0
2
11 10 9
11
TM
1. O
2. I
— Cascade Data Output
is a 12-bit cascade output
2
for data input, a HIGH to
TM
10
11-0
S
F
F
F
F
F
F
·
·
·
. When enabling the LF
15
15
16
17
29
30
31
Input Data
2
NPUT
UTPUT
on one device should
9
S
F
F
F
F
F
F
·
·
·
3
14
14
15
16
28
29
30
11-0
F
TM
S
F
F
F
F
F
F
ORMATS
F
2
2
·
·
·
13
14
15
27
28
29
13
of another
2
ORMATS
Pause
2
1
TM
1
11-0
on the
2
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
0
0
is
TM
Vertical Digital Image Filter
When PAUSE is HIGH, the LF Inter-
face
until PAUSE is returned to a LOW
state. This effectively allows the user
to load coefficients and control regis-
ters at a slower rate than the master
clock (see the LF Interface
for a full discussion).
CEN — Coefficient Address Enable
When CEN is LOW, data on CA
latched into the Coefficient Address
Register on the rising edge of CLK.
When CEN is HIGH, data on CA
not latched and the register’s contents
will not be changed.
F
F
F
F
S
F
F
·
·
·
F
10
22
23
24
8
8
9
Video Imaging Products
IGURE
TM
(Sign)
(Sign)
11 10 9
F
F
F
2
S
F
F
F
2
31 30 29
·
·
·
0
21
22
23
7
8
9
loading sequence is halted
7
20
Accumulator Output
2
3. A
Coefficient Data
2
1
19
2
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
· · ·
2
2
CCUMULATOR
18
2
2
2
F
F
F
9
S
F
F
F
2
9/19/2005–LDS.3330-N
·
·
·
9
16
17
18
2
3
4
2
2
TM
2
1
10
1
10
LF3330
F
F
F
S
F
F
F
·
·
·
2
F
section
15
16
17
1
2
3
1
2
0
11
ORMAT
0
11
7-0
F
F
F
7-0
S
F
F
F
·
·
·
14
15
16
0
0
1
2
is
is