ak4317 ETC-unknow, ak4317 Datasheet - Page 9

• Manufacturer Part Number: ak4317
• Description: 18bit Scf Dac With Att & Mixer
• Manufacturer: ETC-unknow

ASAHI KASEI
The external clocks which are required to operate the AK4317 are MCLK, LRCK, BICK. The master
clock(MCLK)should be synchronized with LRCK but the phase is not critical. The MCLK is used to
operate the digital interpolation filter and the delta-sigma modulator. The frequency of MCLK is
determined by the sampling rate (LRCK) and CKS pin. Table 1 illustrates corresponding clock
frequencies. When the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). Refer to
Figure 1 .
All external clocks(MCLK,BICK,LRCK) should always be present whenever the AK4317 is in normal
operation mode(PD="H"). If these clocks are not provided, the AK4317 may draw excess current because
the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4317
should be in the power-down mode(PD="L"). After exiting reset at power-up etc., the AK4317 is in power-
down mode until MCLK and LRCK are input.
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Four serial data modes which are
compatible with AK4319 are supported and selected by the DIF0 and DIF1 pins as shown in Table 2 . In
all modes the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK.
Mode 2 can be used for 16 MSB justified formats by zeroing the unused LSBs.
0172-E-01
Audio Serial Interface Format
System Clock
DIF1 DIF0
0
0
1
1
0
1
0
1
Clock
LRCK (fs)
BICK
MCLK
0: 16bit LSB Justified
1: 18bit LSB Justified
2: 18bit MSB Justified
3: I
2
S Compatible
Table 2 . Serial Data Modes
Table 1 . System Clocks
Figure 1 . MCLK divider
CKS="L"
CKS="H"
OPERATION OVERVIEW
Mode
- 9 -
frequency
8
k 50kHz
256fs
384fs
64fs
or 32fs
BICK
32fs
36fs
36fs
36fs
Figure 2
Figure 2
Figure 3
Figure 4
Figure
[AK4317]
1997/5