xr16m680 Exar Corporation, xr16m680 Datasheet - Page 13
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xr16m680
Manufacturer Part Number
xr16m680
Description
1.62v To 3.63v High Performance Uart With 32-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16M680.pdf
(57 pages)
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REV. 1.0.0
The M680 has independent Baud Rate Generators (BRGs) with prescalers for the transmitter and receiver.
The prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to
divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG
further divides this clock by a programmable divisor between 1 and (2
16) to obtain a 16X or 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the
transmitter for data bit shifting and receiver for data sampling. For transmitter and receiver, the M680 provides
respective BRG divisors. The BRG divisor (DLL, DLM, and DLD registers) defaults to the value of ’1’ (DLL =
0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during initialization
to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and the DLD
registers provides the fractional part of the divisor. The four lower bits of the DLD are used to select a value
from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator
Registers DLL, DLM and DLD provides the capability for selecting the operating data rate.
standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used
(MCR bit-7 = 1), the output data rate will be 4 times less than that shown in
data rates would double. And at 4X sampling rate, they would quadruple. Also, when using 8X sampling mode,
please note that the bit-time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number.
When using a non-standard data rate crystal or external clock, the divisor value can be calculated with the
following equation(s):
The closest divisor that is obtainable in the M680 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
The XR16M680 has two independent sets of TX and RX baud rate generator. Please see the
RX can work in different baud rate by setting DLD, DLL and DLM register. For example, TX can transmit data
to the remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate
setting, please
page
2.7
2.7.1
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
39..
Programmable Baud Rate Generator with Fractional Divisor
Independent TX/RX BRG
See ”Section 4.13, Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write” on
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
DLL = TRUNC(Required Divisor) & 0xFF
DLM = TRUNC(Required Divisor) >> 8
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
13
16
- 0.0625) in increments of 0.0625 (1/
Table
3. At 8X sampling rate, these
Table 3
Figure
XR16M680
shows the
8. TX and