xr16m2750 Exar Corporation, xr16m2750 Datasheet
xr16m2750
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xr16m2750 Summary of contents
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... OTE 1 Covered by U.S. Patent #5,649,122 APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls F 1. XR16M2750 B D IGURE LOCK IAGRAM A2:A0 D7:D0 IOR# IOW# CSA# CSB# 8-bit Data INTA Bus INTB ...
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... XR16M2750IL32 32-pin QFN XR16M2750IM48 48-Lead TQFP XR16M2750 6 48-pin TQFP XR16M2750 21 4 32-pin QFN ACKAGE PERATING EMPERATURE -40°C to +85°C -40°C to +85°C 2 REV. 1.0.0 RESET 36 35 DTRB# 34 DTRA# ...
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... RX FIFO/RHR status for receive channel A. See used, leave it unconnected. O UART channel B Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel B. See used, leave it unconnected. 3 XR16M2750 ESCRIPTION Table not Table not Table not ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Pin Description 32-QFN 48-TQFP N AME RXRDYB MODEM OR SERIAL I/O INTERFACE TXA 5 7 RXA 4 5 RTSA CTSA DTRA DSRA CDA RIA OP2A TXB YPE ESCRIPTION O UART channel B Receiver Ready (active low). This output provides the RX FIFO/RHR status for receive channel B ...
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... GND on the PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be solder mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad. 5 XR16M2750 ESCRIPTION Table 16 ). ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Pin Description 32-QFN 48-TQFP N AME N. 12, 24, 25, 37 Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain YPE ESCRIPTION No Connection. 6 REV. 1.0.0 ...
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... FIFO trigger levels, FIFO level counters, infrared encoder and decoder (IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of divide and data rate Mbps with 8X sampling clock rate or 4 Mbps in the 16X rate. The XR16M2750 is a 1.62 to 3.63V device. The M2750 is fabricated with an advanced CMOS process. ...
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... To read the identification code from the part required to set the baud rate generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DLM will provide 0x0A for the XR16M2750 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means revision A. ...
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... HIGH to LOW transition when FIFO reaches the trigger level, or time-out occurs. HIGH = FIFO empty. LOW to HIGH transition when FIFO empties. LOW = FIFO empty. LOW = FIFO has at least 1 empty location. HIGH = at least 1 byte in FIFO. HIGH = FIFO is full. 9 XR16M2750 through 22. DMA M AND ODE ) NABLED FCR Bit (DMA Mode Enabled) ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.7 INTA and INTB Outputs The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see through 22 ...
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... ROUND ( rounded towards the closest integer. For example, ROUND (7. and ROUND (9.9) = 10. A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 0x0078. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO DLM = TRUNC(Required Divisor) >> 8 DLL = TRUNC(Required Divisor) & 0xFF 11 XR16M2750 Figure 4). The programmable Baud Table 5. At ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IGURE AUD ATE ENERATOR Crystal XTAL1 Osc/ XTAL2 Buffer ABLE YPICAL DATA RATES WITH A Required D IVISOR FOR Output Data 16x Clock O Rate (Decimal) 400 3750 2400 625 4800 312.5 9600 156 ...
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... IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO -FIFO M ODE Transmit Holding Register THR Interrupt (ISR bit-1) (THR) Enabled by IER bit-1 M Transmit Shift Register (TSR XR16M2750 TXNOFIFO1 ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IGURE RANSMITTER PERATION IN Transmit Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control 16X or 8X Clock (EMSR bit-7) 2.11 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR) ...
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... RTS# de-asserts when data fills above the flow 24 control trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-1. Receive Data Figure 9 Table XR16M2750 ive cte Inte rru ODE Receive Data Characters RXFIFO1 ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.12 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features is enabled to fit specific application requirement (see • ...
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... RXA TXB RTSA# CTSB# TXA RXB CTSA# RTSB# ON OFF 7 ON OFF 8 Restart 6 Suspend 9 RTS High RTS Low 5 Threshold Threshold 17 XR16M2750 Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level FIFO 12 Trigger Level RTSCTS1 ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.15 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M2750 will halt transmission (TX) as soon as the current character has completed transmission ...
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... Figure 11 below. Figure 11 RANSMIT ATA NCODING AND Character Data Bits Bit Time 3/16 Bit Time Bit Time 1/16 Clock Delay Data Bits Character 19 XR16M2750 ECEIVE ATA ECODING 1 1/2 Bit Time IrEncoder IRdecoder- ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.19 Sleep Mode with Auto Wake-Up The M2750 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied for the M2750 to enter sleep mode: no interrupts pending for both channels of the M2750 (ISR bit ■ ...
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... TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ACK IN HANNEL AND VCC (THR/FIFO) MCR bit-4=1 (RHR/FIFO) VCC RTS# CTS# VCC DTR# DSR# OP1# RI# VCC OP2# CD# 21 XR16M2750 TXA/TXB RXA/RXB RTSA#/RTSB# CTSA#/CTSB# DTRA#/DTRB# DSRA#/DSRB# RIA#/RIB# OP2A#/OP2B# CDA#/CDB# ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each of the UART channel in the M2750 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the channel. The complete register set is shown on Table 8 ...
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... Bit-4 Bit-3 LSR Auto Auto Auto Error RS485 RTS RTS Inter- Output Hyst. Hyst. rupt. Inversion bit-3 bit-2 Imd/Dly# Bit-6 Bit-5 Bit-4 Bit-3 23 XR16M2750 EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 RX Line TX RX LCR[7]=0 Stat ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ABLE NTERNAL EGISTERS DDRESS EG EAD A2- AME RITE DLL RD/WR Bit DLM RD/WR Bit DLD RD/ DREV RD Bit DVID TRG WR Bit ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M2750 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IER[4]: Sleep Mode Enable (requires EFR bit • Logic 0 = Disable Sleep Mode (default). • Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details. IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • ...
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... LSR (Receiver Line Status Register RXRDY (Receive Data Time-out RXRDY (Received Data Ready TXRDY (Transmit Ready MSR (Modem Status Register RXRDY (Received Xoff or Special character CTS#, RTS# change of state None (default) 27 XR16M2750 L EVEL S OURCE OF INTERRUPT Table 9). ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic transmit FIFO reset (default). • Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not cleared or altered) ...
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... Programmable via TRG register. FCTR[ BIT-0 W ORD LENGTH 0 5 (default XR16M2750 L S EVEL ELECTION T RANSMIT T C RIGGER OMPATIBILITY L EVEL 1 (default) 16C550, 16C2550, 16C2552, 16C554, 16C580 16 16C650A 16C654 Programmable 16L2752, 16C2850, ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check ...
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... Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation. The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and the M2750 is programmed to use the Xon/Xoff flow control. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Figure 31 XR16M2750 12. ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4=1) • Logic 0 = Enable the standard modem receive and transmit input/output interface (default). • Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the infrared encoder/decoder ...
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... Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 33 XR16M2750 ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO MSR[6]: RI Input Status Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. ...
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... EFR bit-4 before it can be accessed. FRACTIONAL DIVISOR” ON PAGE 11. 4.14 Device Identification Register (DVID) - Read Only This register contains the device ID (0x0A for XR16M2750). Prior to reading this register, DLL and DLM should be set to 0x00 (DLD = 0xXX). 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T ...
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... Feature Control Register (FCTR) - Read/Write This register controls the XR16M2750 functions that are not available in ST16C2450 or ST16C2550. FCTR[1:0]: RTS Hysteresis User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to “0” to select the next trigger level for hardware flow control. See FCTR[2]: IrDa RX Inversion • ...
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... TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T 14 ABLE RIGGER ABLE ELECT FCTR T ABLE Table-A (TX/RX) 1 Table-B (TX/RX) 0 Table-C (TX/RX) 1 Table-D (TX/RX) Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes 37 XR16M2750 ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T ABLE EFR -3 EFR -2 EFR BIT BIT ONT ONT EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, and DLD to be modified ...
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... Data transmission resumes when CTS# returns LOW. 4.19.1 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. For more details, see Table 6. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 39 XR16M2750 ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T 16: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They do not reset when the Reset Pin is asserted. DLD Bits 7-0 = 0x00 ...
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... L IMITS IMITS 1.8V 2. -0.3 0.3 -0.3 0.4 1.4 VCC 2.0 VCC -0.3 0.2 -0.3 0.5 1.4 VCC 1.8 VCC 0.4 0.4 1.8 1.4 ±10 ±10 ±10 ± 1 XR16M2750 4 Volts GND-0.3V to VCC+0. - -65 to +150 C 500 C/W, theta- C C/W, theta- C/W L IMITS 3. NITS ONDITIONS -0.3 0.6 V 2.4 VCC V -0.3 0.7 V 2.0 VCC V 0 ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Floating inputs will result in sleep currents in the mA range. For PowerSave feature that isolates address, data and control signals, please see the XR16M2751 datasheet. AC ELECTRICAL CHARACTERISTICS U : TA=-40 NLESS OTHERWISE NOTED S P YMBOL ARAMETER XTAL1 ...
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... TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO =1.62 - 3.63V IMITS IMITS 1.8V ± 10% 2.5V ± 10 16X data rate T ECLK T ECH 43 XR16M2750 F LOAD WHERE APPLICABLE L IMITS 3.3V ± 10% U NIT Bclk ECL ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 14 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI IGURE ATA US EAD IMING A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- & B ...
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... Stop D0:D7 Bit T T SSR SSR 1 Byte 1 Byte in RHR in RHR T T SSR SSR Active Active Data Data Ready Ready XR16M2750 Valid Address Valid Data 16Write C A & B HANNELS D0:D7 T SSR 1 Byte in RHR T SSR Active Data Ready ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 18 & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data into THR) *INT is cleared when the ISR is read or when data is loaded into the THR. ...
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... D0: SSI T SSR T [FIFO M , DMA M IMING ODE Stop Bit D0:D7 D0:D7 T D0: trigger level T WRI 47 XR16M2750 ] C A & B FOR HANNELS S D0: D0: FIFO drops below RX Trigger Level FIFO Empties T T RRI RR RXFIFODMA & B ODE ISABLED FOR HANNELS ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 22 & I IGURE RANSMIT EADY NTERRUPT Stop Start Bit Bit TX S D0: D0:D7 (Unloading) IER[1] ISR Read enabled INT* TXRDY# IOW# (Loading data into FIFO) *INT cleared when the ISR is read or when TX FIFO fills up to trigger level. ...
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... INCHES MILLIMETERS MIN MAX MIN 0.039 0.047 1.00 0.002 0.006 0.05 0.037 0.041 0.95 0.007 0.011 0.17 0.004 0.008 0.09 0.346 0.362 8.80 0.272 0.280 6.90 0.020 BSC 0.50 BSC 0.018 0.030 0.45 0° 7° 0° 49 XR16M2750 α L MAX 1.20 0.15 1.05 0.27 0.20 9.20 7.10 0.75 7° ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.193 0.201 4.90 0.138 ...
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... Copyright 2007 EXAR Corporation Datasheet August 2007. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO D ESCRIPTION NOTICE 51 XR16M2750 ...
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... REV. 1.0.0 GENERAL DESCRIPTION................................................................................................ 1 A .............................................................................................................................................. 1 PPLICATIONS F .................................................................................................................................................... 1 EATURES F 1. XR16M2750 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT O .............................................................................................................................. 2 RDERING INFORMATION PIN DESCRIPTIONS ........................................................................................................ 3 1.0 PRODUCT DESCRIPTION ...................................................................................................................... 7 2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 8 2.1 CPU INTERFACE ................................................................................................................................................ XR16M2750 IGURE ATA US NTERCONNECTIONS 2.2 DEVICE RESET ................................................................................................................................................... 8 2.3 DEVICE IDENTIFICATION AND REVISION ....................................................................................................... 8 2 ...
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... XR16M2750 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 26 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... FIFO T ABLE RANSMIT AND ECEIVE 4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 29 T 11: P ........................................................................................................................................................ 30 ABLE ARITY SELECTION 4 ...