xr16m770il32 Exar Corporation, xr16m770il32 Datasheet - Page 41

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xr16m770il32

Manufacturer Part Number
xr16m770il32
Description
1.62v To 3.63v High Performance Uart With 64-byte Fifo
Manufacturer
Exar Corporation
Datasheet
REV. 1.0.0
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the next upper trigger level/hysteresis level. RTS# will return LOW when FIFO data
falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (LOW) before the
auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is
disabled.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see
enabled.
4.18
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
See ”Section 2.15.1, Auto Address Detection” on page 19.
Table
5. The xoff2 is also used as auto address detect register when the auto 9-bit mode
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
41
XR16M770

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