xr16v2650im Exar Corporation, xr16v2650im Datasheet
xr16v2650im
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xr16v2650im Summary of contents
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MAY 2007 GENERAL DESCRIPTION 1 The XR16V2650 (V2650 high performance dual universal asynchronous receiver and transmitter (UART) with 32 bytes TX and RX FIFOs. The device operates from 2.25 to 3.6 volts with 5 Volt tolerant inputs and ...
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... SSIGNMENT RXB RXA TXRDYB# TXA TXB OP2B# CSA# CSB# NC RXB RXA TXA TXB CSA# CSB# ORDERING INFORMATION ART UMBER XR16V2650IL32 32-Pin QFN XR16V2650IM 48-Lead TQFP XR16V2650 6 48-pin TQFP XR16V2650 4 21 ...
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REV. 1.0.2 PIN DESCRIPTIONS Pin Description 32-QFN 48-TQFP N AME DATA BUS INTERFACE ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO Pin Description 32-QFN 48-TQFP N AME RXRDYB MODEM OR SERIAL I/O INTERFACE TXA 5 7 RXA 4 5 RTSA CTSA DTRA# ...
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REV. 1.0.2 Pin Description 32-QFN 48-TQFP N AME RTSB CTSB DTRB DSRB CDB RIB OP2B ANCILLARY SIGNALS XTAL1 10 13 ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR16V2650 (V2650) provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data ...
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REV. 1.0.2 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The V2650 data interface supports the Intel compatible types ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO registers, but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in Table 1. CSA 2.6 Channel A and B Internal Registers Each ...
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REV. 1.0.2 2.8 INTA and INTB Outputs The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see through 22. ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency tolerance) connected externally between ...
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REV. 1.0 IGURE AUD ATE ENERATOR Crystal XTAL1 Osc/ XTAL2 Buffer ABLE YPICAL DATA RATES WITH A Required D IVISOR FOR Output Data 16x Clock O Rate (Decimal) 400 3750 2400 625 ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO 2.11 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 32 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with ...
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REV. 1.0 IGURE RANSMITTER PERATION IN Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg.) Auto Software Flow Control 16X Clock (DLD[5:4]) 2.12 Receiver The receiver ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO IGURE ECEIVER PERATION IN NON rro ...
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REV. 1.0.2 2.13 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO F 10. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 ...
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REV. 1.0.2 2.16 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the V2650 will halt transmission (TX) as soon as ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO 2.18 Infrared Mode The V2650 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a ...
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REV. 1.0.2 2.19 Sleep Mode with Auto Wake-Up The V2650 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO 2.20 Internal Loopback The V2650 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions ...
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REV. 1.0.2 3.0 UART INTERNAL REGISTERS Each of the UART channel in the V2650 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the channel. The complete register set ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO . T 9: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR ...
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REV. 1.0 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE EFR RD/WR Auto CTS Enable XON1 RD/WR Bit ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the selected trigger level ...
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REV. 1.0.2 4.4 Interrupt Status Register (ISR) - Read-Only The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO ISR[0]: Interrupt Status • Logic interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. • Logic interrupt ...
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REV. 1.0.2 FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1) (logic 0 = default, TX trigger level = 1) These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the number ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and RX Parity ...
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REV. 1.0.2 LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space", LOW state). This condition remains, until disabled by setting LCR bit ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO MCR[5]: Xon-Any Enable (requires EFR bit-4=1) • Logic 0 = Disable Xon-Any function (default). • Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation. The ...
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REV. 1.0.2 LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO MSR[5]: DSR Input Status Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input ...
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REV. 1.0.2 EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. T ABLE EFR -3 EFR -2 EFR BIT BIT C ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when ...
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REV. 1.0.2 T 15: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They do not reset when the Reset Pin ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) Thermal Resistance (32-QFN) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS O ...
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REV. 1.0.2 AC ELECTRICAL CHARACTERISTICS -40 NLESS OTHERWISE NOTED S P YMBOL ARAMETER XTAL1 UART Crystal Oscillator ECLK External Clock T External Clock Time Period ECLK T Address Setup Time AS T Address Hold Time AH ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO F 13 IGURE LOCK IMING VIH External Clock VIL F 14 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT ...
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REV. 1.0 IGURE ATA US EAD IMING A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ATA US RITE IMING A0-A2 Valid Address T AS ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO F 17 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX ...
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REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading data out of RX FIFO) F ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO F 21 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in TX FIFO ...
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REV. 1.0.2 PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL HIGH PERFORMANCE DUART ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 mm) Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN MAX ...
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... Updated "AC electrical characteristic" table and pin description table. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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XR16V2650 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO GENERAL DESCRIPTION ................................................................................................ 1 A ............................................................................................................................................... 1 PPLICATIONS F .................................................................................................................................................... 1 EATURES F 1. XR16V2650 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT ................................................................................................................................ 2 ...
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REV. 1.0.2 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 25 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 26 ...