xr16v598 Exar Corporation, xr16v598 Datasheet - Page 13

• Manufacturer Part Number: xr16v598
• Description: 2.25v To 3.6v High Performance Octal Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
The THR and RHR register addresses for channel 0 to channel 7 are shown in
RHR for channels 0 to 7 are located at address 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60 and 0x70
respectively. Transmit data byte is loaded to the THR when writing to that address and receive data is
unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550
compatible in 8-bit format, so each bus operation can only write or read in bytes.
F
F
2.9
IGURE
IGURE
7. R
8. R
THR and RHR Register Locations
16X or 8X or 4X Clock
Receive Data
Byte and Errors
16 bytes by 11-bit
ECEIVER
ECEIVER
FIFO
wide
16X or 8X or 4X Clock
O
O
PERATION IN NON
PERATION IN
and Errors
Data Byte
Receive
Receive Data Shift
Register (RSR)
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
Data FIFO
FIFO
Receive
Receive
Data
LSR bits
Tags in
-FIFO M
Error
4:2
AND
Receive Data Shift
Register (RSR)
A
Validation
UTO
Holding Register
ODE
Data Bit
Data fills to 14
FIFO Trigger=8
Receive Data
Data falls to 4
(RHR)
Example:
RTS F
13
LOW
Enable by EFR bit-6=1, MCR bit-1.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
RTS# de-asserts when data fills above the flow
- RX FIFO trigger level selected at 8 bytes
desired FIFO trigger level.
control trigger level to suspend remote transmitter.
FIFO is Enabled by FCR bit-0=1
Validation
RHR Interrupt (ISR bit-2) programmed for
Data Bit
C
ONTROL
(See Note Below)
RHR Interrupt (ISR bit-2)
M
ODE
Receive Data Characters
Receive Data Characters
Table 5
RXFIFO1
below. The THR and
RXFIFO1
XR16V598