xr16v698 Exar Corporation, xr16v698 Datasheet
xr16v698
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xr16v698 Summary of contents
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... TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO JANUARY 2008 GENERAL DESCRIPTION 1 The XR16V698 (698 2.25V to 3.6V octal Universal Asynchronous Receiver and Transmitter (UART) with 5V tolerant inputs. The highly integrated device is designed for high bandwidth requirement in communication systems. The global interrupt source ...
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... ORDERING INFORMATION ART UMBER XR16V698IQ100 100-Lead QFP XR16V698 100-QFP ACKAGE PERATING EMPERATURE -40°C to +85°C 2 REV. 1.0.2 ...
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... I XR16V698 device. When 16/68# pin is LOW, this input becomes the read and write strobe (active LOW) for the Motorola bus interface. Global interrupt output from XR16V698 (open drain, active LOW). This output INT requires an external pull-up resistor (47K-100K ohms) to operate properly. It may be shared with other devices in the system to form a single interrupt line to the host pro- cessor and have the software driver polls each device for the interrupt status ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO AME IN YPE UART channel 0 Ring Indicator or general purpose input (active LOW). RI0 UART channel 1 Transmit Data or infrared transmit data. TX1 85 O UART channel 1 Receive Data or infrared receive data. Normal RXD input idles ...
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... UART channel 6 Data Set Ready or general purpose input (active LOW). See DSR6 description of DSR0# pin. UART channel 6 Carrier Detect or general purpose input (active LOW). CD6 UART channel 6 Ring Indicator or general purpose input (active LOW). RI6 UART channel 7 Transmit Data or infrared transmit data. TX7 ESCRIPTION 5 XR16V698 ...
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... I a hardware reset (RST#) or soft-reset (register RESET). It can be used to start up all 8 UARTs in the infrared mode. The sampled logic state is transferred to MCR bit-6 in the UART. Reset (active LOW). The XR16V698 does not have a Power-on reset. Therefore, a RST hardware reset must be issued using this pin during power-up. The configuration and UART registers are reset to default values, see Intel or Motorola data bus interface select ...
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... REV. 1.0.2 1.0 DESCRIPTION The XR16V698 (698) integrates the functions of 8 enhanced 16550 UARTs, a general purpose 16-bit timer/ counter and an on-chip oscillator. The device configuration registers include a set of four consecutive interrupt source registers that provides interrupt-status for all 8 UARTs, timer/counter and a sleep wake up indicator. ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 2.4 INT# Ouput The INT# interrupt output changes according to the operating mode and enhanced features setup. and 3 summarize the operating behavior for the transmitter and receiver. T ABLE Auto RS-485 FCR B Mode (FIFO D NO ...
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... ROUND ( rounded towards the closest integer. For example, ROUND (7. and ROUND (9.9) = 10. A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 0x0078 0.0625) in increments of 0.0625 (1/16) to shows the standard data rates available with a 24MHz crystal or DLM = TRUNC(Required Divisor) >> 8 DLL = TRUNC(Required Divisor) & 0xFF 9 XR16V698 ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO IGURE AUD ATE ENERATOR XTAL1 Crystal Osc/ XTAL2 Buffer ABLE YPICAL DATA RATES WITH A Required D 16x IVISOR FOR Output Data Clock O Rate (Decimal) 400 3750 2400 625 4800 312.5 9600 156 ...
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... Register or 4XMODE Register) internal clock. A bit time is 16 -FIFO M ODE Transmit Holding Register (THR) THR Interrupt (ISR bit-1) Enabled by IER bit-1 M Transmit Shift Register (TSR XR16V698 16X S AMPLING DLD ROGRAM ROGRAM ATA RROR (HEX) V (HEX)) R (%) ALUE ATE ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 2.7.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the amount of data in the FIFO falls below its programmed trigger level ...
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... FIFO is Enabled by FCR bit-0=1 RTS# de-asserts when data fills above the flow Data fills to 24 control trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-1. Receive Data 13 XR16V698 Receive Data Characters RXFIFO1 M ODE Receive Data Characters RXFIFO1 Table 5 below. The THR and ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO . ABLE RANSMIT AND THR and RHR Address Locations For CH0 to CH7 (16C550 Compatible) CH0 0x00 Write THR CH0 0x00 Read RHR CH1 0x10 Write THR CH1 0x10 Read RHR CH2 0x20 Write THR ...
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... CTS#/DSR# pin makes a transition: ISR bit-5 will be set to a logic 1, and UART will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS#/DSR# input returns LOW, indicating more data may be sent. Figure 9): 15 XR16V698 ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO RTS/DTR CTS/DSR F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts 4 RXA FIFO ...
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... Registers corresponds to the LSB bit for the receive character. (See Table 17), the 698 compares one or two sequential receive data UTO ON OFF OFTWARE LOW OFF HARACTER S ENT ( ) CHARACTERS IN RX FIFO 8* 16* 24* 28* 17 XR16V698 ONTROL HARACTER S ENT ( ) CHARACTERS IN RX FIFO ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 2.13 Auto RS-485 Half-duplex Control The auto RS-485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR bit-5. It also changes the behavior of the transmit empty interrupt (see (LOW) after a specified delay indicated in MSR[7:4] following the last stop bit of the last character that has been transmitted. This helps in turning around the transceiver to receive the remote station’ ...
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... Receive IR Pulse (RX pin) RX Data RANSMIT ATA NCODING AND ECEIVE Character Data Bits Bit Time 3/16 Bit Time Bit Time 1/16 Clock Delay Data Bits Character 19 XR16V698 D D ATA ECODING 1 0 1/2 Bit Time IrEncoder IRdecoder- ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 2.15 Sleep Mode with Auto Wake-Up The 698 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied for the 698 to enter sleep mode: no interrupts pending for all 8 channels of the 698 (ISR bit ■ ...
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... The TX pin is held at HIGH or mark condition while RTS# and DTR# are de-asserted (HIGH), and CTS#, DSR# CD# and RI# inputs are ignored IGURE NTERNAL OOP B ACK VCC Transmit Shift Register MCR bit-4=1 Receive Shift Register VCC RTS# CTS# VCC DTR# DSR# OP1# RI# OP2# CD# 21 XR16V698 TX [7:0] RX [7:0] RTS# [7:0] CTS# [7:0] DTR# [7:0] DSR# [7:0] RI# [7:0] CD# [7:0] ...
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... XR16V698 REGISTERS The XR16V698 octal UART register set consists of the Device Configuration Registers that are accessible directly from the data bus for programming general operating conditions of the UARTs and monitoring the status of various functions. These functions include all 8 channel UART’s interrupt control and status, 16-bit general purpose timer control and status, sleep mode, soft-reset, and device identification and revision ...
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... UART channel 4 Registers 0x50 - 0x5F UART channel 5 Registers 0x60 - 0x6F UART channel 6 Registers 0x70 - 0x7F UART channel 7 Registers 0x80 - 0x8F Device Configuration Registers , and device identification and revision XR16V698 R S ABLE EGISTER ETS S R PACE EFERENCE Table & ...
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... REGB 0 3.1.1 The Global Interrupt Source Registers The XR16V698 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1, INT2 and INT3]. The four registers are in the device configuration register address space. INT3 [0x00] All four registers default to logic zero (as indicated in square braces) for no interrupt pending. All 8 channel interrupts are enabled or disabled in each channel’ ...
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... INT2 Register Channel-4 Channel-3 Channel-2 Bit Bit Bit Bit Bit Bit Bit Bit Bit Ch-7 Bit-7 25 XR16V698 Bit-0 Ch-0 Table 9 shows the 3 bit INT1 Register Channel-1 Channel-0 Bit Bit Bit Bit Bit Bit Bit INT0 Register Ch-6 Ch-5 Ch-4 ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO T 9: UART C ABLE HANNEL Bit Bit Bit P RIORITY None or wake-up indicator RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the RX FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR register. ...
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... TIMERMSB and TIMERLSB (16-bit Value) 1 TMRCK 0 OSC. CLOCK Clock Select Start/Stop TIMERCNTL Single shot/Re-triggerable COMMANDS Timer Interrupt Enable/ Disable T 10: TIMER C C ABLE ONTROL OMMANDS Figure 15, where the time between successive time-outs (in re- Timer Interrupt 16-Bit Timer/Counter 27 XR16V698 1 Timer Interrupt No Interrupt 0 ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO F 15 IGURE NTERRUPT UTPUT IN Timer Started One-shot Mode Re-triggerable Mode 3.1.3 8XMODE [7:0] (default 0x00) Each bit selects sampling rate for that UART channel, for example, bit-0 is channel 0. This register associates with 4XMODE register to decide the sampling rate (16X 4X). When 4XMODE [7:0] = 0x00, Logic 0 (default) selects normal 16X sampling with logic one selects 8X sampling rate ...
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... DVID register provides device identification. A return value of 0x68 from this register indicates the device is a XR16V698. The DREV register returns a 8-bit value of 0x01 for revision A, 0x02 for revision B and so on. This information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 3.2 UART Channel Configuration Registers The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper 8 addresses. The 8 sets of UART configuration registers are decoded using address lines shown below ...
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... RX Input Enable Auto Special Enable Software RTS/DTR Char Flow Cntl IER [7:5], Enable Select ISR [5:4], Bit-3 FCR[5:4], MCR[7:5, 3:2] MSR[7: XR16V698 . S EFR B -4. HADED BITS ARE ENABLED OMMENT Bit-2 Bit-1 Bit-0 LCR[7]=0 Bit-2 Bit-1 ...
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... W Bit XON2 W Bit MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR16V698. They are present for 16C550 compat- OTE Figure 11 ibility during Internal loopback, see 4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 Receive Holding Register (RHR) - Read Only SEE”RECEIVER” ON PAGE 12.. ...
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... TX FIFO becomes empty. When auto RS-485 mode is enabled (FCTR bit-5 = 1), the second interrupt is delayed until the transmitter (both the TX FIFO and the TX Shift Register) is empty. • Logic 0 = Disable Transmit Ready Interrupt (default). • Logic 1 = Enable Transmit Ready Interrupt. 33 XR16V698 ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO IER[0]: RX Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode. • ...
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... RXRDY (Received Xon/Xoff or Special character CTS#/DSR#, RTS#/DTR# change of state None (default) or wake-up indicator and “Section 4.4.2, Interrupt Clearing:” on page 34 Table 14 Table 14 35 XR16V698 L EVEL S OURCE OF THE INTERRUPT Table 13). See “Section for details. shows the complete selections. below shows the selections. ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO FCR[3]: DMA Mode Select This bit has no effect since TXRDY and RXRDY pins are not available in this device provided for legacy software compatibility. • Logic 0 = Set DMA to mode 0 (default). • Logic 1 = Set DMA to mode 1. ...
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... Logic parity bit is generated during the transmission while the receiver checks for parity error of the data character received ABLE ARITY ROGRAMMING -4 LCR ARITY SELECTION Odd parity 1 1 Even parity 0 1 Force parity to mark, “1” Force parity to space, “0” 37 XR16V698 No parity ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. ...
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... Logic FIFO error (default). • Logic indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or break indication is in the FIFO data. This bit clears when there are no more errors in the FIFO. 39 XR16V698 ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO LSR[6]: Transmitter Empty Flag This bit is the Transmitter Empty indicator. This bit is set to a logic 1 whenever both the transmit FIFO (or THR, in non-FIFO mode) and the transmit shift register (TSR) are both empty set to logic 0 whenever either the TX FIFO or TSR contains a data character ...
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... RS-485 transceiver. These 4 bits select from bit-time delay after the end of the last stop-bit of the last transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in long-cable networks. Table 16 shows the selection. The bits are enabled by EFR bit-4. 41 XR16V698 ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO T 16: A RS-485 H ABLE UTO ALF MSR[7] MSR[ MSR[3]: Transmitter Disable This bit can be used to disable the transmitter by halting the Transmit Shift Register (TSR). When this bit is set to a ’ ...
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... It also changes the transmitter interrupt from transmit holding to transmit shift register (TSR) empty. FCTR[4]: Infrared RX Input Logic Select • Logic 0 = Select RX input as active HIGH encoded IrDA data, normal, (default). • Logic 1 = Select RX input as active LOW encoded IrDA data, inverted. FCTR [3:0] - Reserved “Section 2.13, Auto RS-485 Half-duplex Control” on page 18 43 XR16V698 ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 4.13 Enhanced Feature Register (EFR) - Read/Write Enhanced features are enabled or disabled using this register. Bits 3:0 provide single or dual consecutive character software flow control selection (see are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that whenever changing the flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting ...
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... Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2 Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 45 XR16V698 Table ECEIVE OFTWARE LOW ONTROL ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 4.15 XCHAR Register - Read Only This register gives the status of the last sent control character (xon or xoff) and the last received control character (xon or xoff). This register will be reset to 0x00 if, at anytime, the Software Flow Control is disabled. ...
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... TFTRG Bits 7-0 = 0x00 RFCNT Bits 7-0 = 0x00 RFTRG Bits 7-0 = 0x00 XCHAR Bits 7-0 = 0x00 XON1 Bits 7-0 = 0x00 XON2 Bits 7-0 = 0x00 XOFF1 Bits 7-0 = 0x00 XOFF2 Bits 7-0 = 0x00 T 18: UART R C ABLE ESET ONDITIONS I/O SIGNALS TX[7:0] IRTX[7:0] RTS#[7:0] DTR#[7:0] 47 XR16V698 RESET STATE HIGH LOW HIGH HIGH ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (14x20x3.0mm 100-QFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS TA (-40 to +85 C for industrial grade package), Vcc is 2.25V to 3.6V ...
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... XR16V698 3.3V U NITS MHz 60 MHz Bclk ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA (-40 to +85 C for industrial grade package), Vcc is 2.25V to 3.6V Load where applicable S P YMBOL ARAMETER T Delay From Stop To Interrupt SI T Delay From IOW# To Reset Interrupt WRI T Reset Pulse ...
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... RDH T RDV Valid Data 16 Mode (Intel) Data Bus Read Timing WDH T WDS Valid Data 16 Mode (Intel) Data Bus Write Timing 51 XR16V698 Valid Address RDH Valid Data 16Read Valid Address WDH T WDS Valid Data ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO F 17 IGURE ODE OTOROLA A0-A7 T ADS CS# T RWS R/W# T RDA D0-D7 A0-A7 T ADS CS# T RWS R/W# T WDS D0- ATA US EAD AND RITE IMING Valid Address T T CSL ADH T CSD T RWH T RDH Valid Data 68 Mode (Motorola) Data Bus Read Timing ...
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... IO R# (Reading data out of RHR) IMING Change of state Change of state T MOD Active T Active [N -FIFO ODE Stop D0:D7 Bit 1 Byte 1 Byte in RHR in RHR XR16V698 Change of state Active Active RSI Active Active Change of state D0:D7 1 Byte in RHR ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO F 20 IGURE RANSMIT NTERRUPT IMING rru ...
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... B e 1.95 mm Form INCHES MILLIMETERS MIN MAX MIN 0.102 0.134 2.60 0.002 0.014 0.05 0.100 0.120 2.55 0.009 0.015 0.22 0.005 0.009 0.13 0.931 0.951 23.65 0.783 0.791 19.90 0.695 0.715 17.65 0.547 0.555 13.90 0.0256 BSC 0.65 BSC 0.026 0.037 0.65 0 ° 7 ° 0 ° 55 XR16V698 α L MAX 3.40 0.35 3.05 0.38 0.23 24.15 20.10 18.15 14.10 0.95 7 ° ...
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... November 2007 Final Datasheet. Updated DC and AC Electrical Specs. 1.0.1 December 2007 Datasheet correction. Removed reference to TXCNT and RXCNT registers since the XR16V698 does not have this feature. 1.0.2 January 2008 Corrected Ordering Part Number. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability ...
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... INFRARED MODE ........................................................................................................................................... IGURE NFRARED RANSMIT ATA 2.15 SLEEP MODE WITH AUTO WAKE-UP ......................................................................................................... 20 2.16 INTERNAL LOOPBACK.................................................................................................................................. ................................................................................................................................................. 21 IGURE NTERNAL OOP ACK 3.0 XR16V698 REGISTERS ....................................................................................................................... 22 F 12. T XR16V698 R IGURE HE EGISTERS DEVICE CONFIGURATION REGISTER SET.................................................................................. 23 3 XR16V698 R S ABLE EGISTER ETS ABLE ...
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... XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 3.1.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX- 00-00).............................................................................................................................................................................. 26 3.1.2.1 TIMERMSB [7:0] AND 3.1.2.2 TIMER [7:0] R ESERVED 3.1.2.3 TIMERCNTL [7:0] R EGISTER T 10: TIMER C C ABLE ONTROL OMMANDS TIMER OPERATION ................................................................................................................................................ ............................................................................................................................................. 27 IGURE IMER OUNTER CIRCUIT F 15. I ...