xr16l2751im Exar Corporation, xr16l2751im Datasheet - Page 15
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xr16l2751im
Manufacturer Part Number
xr16l2751im
Description
2.25v To 5.5v Duart With 64-byte Fifo And Powersave
Manufacturer
Exar Corporation
Datasheet
1.XR16L2751IM.pdf
(52 pages)
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xr
REV. 1.2.2
N
F
F
OTE
IGURE
IGURE
:
Table-B selected as Trigger Table for
Receive Data
Byte and Errors
9. R
10. R
64 bytes by 11-bit
16X Clock
ECEIVER
wide FIFO
ECEIVER
16X or 8X Clock
(EMSR bit-7)
and Errors
O
Data Byte
Receive
O
PERATION IN NON
PERATION IN
Receive Data Shift
Register (RSR)
Data FIFO
Receive
LSR bits
Figure 10
FIFO
Receive
Tags in
Error
Data
4:2
-FIFO M
AND
Receive Data Shift
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
Register (RSR)
Holding Register
A
(
Receive Data
Table 11
ODE
UTO
Data falls to 8
FIFO Trigger=16
Data fills to 24
Validation
Data Bit
(RHR)
Example:
- RX FIFO trigger level selected at 16 bytes
RTS F
15
).
LOW
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Validation
(See Note below)
Data Bit
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
C
ONTROL
RHR Interrupt (ISR bit-2)
M
Receive Data Characters
ODE
Receive Data Characters
RXFIFO1
XR16L2751
RXFIFO1