xr16c864iq Exar Corporation, xr16c864iq Datasheet - Page 16

• Manufacturer Part Number: xr16c864iq
• Description: Quad Uart With Rx/tx Fifo Counters And 128-byte Fifo
• Manufacturer: Exar Corporation

XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
N
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see
If using the Auto RTS interrupt:
The 864 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with the
XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt is
generated when the receive FIFO reaches the programmed RX trigger level. The RTS# pin will not be forced
to a logic 1 (RTS off), until the receive FIFO reaches the upper limit of the hysteresis level. The RTS# pin will
return to a logic 0 after the RX FIFO is unloaded to the lower limit of the hysteresis level. Under the above
described conditions, the 864 will continue to accept data until the receive FIFO gets full. The Auto RTS
function is initiated when the RTS# output pin is asserted to a logic 0 (RTS On).
details for the Auto RTS# Hysteresis levels. Please note that this table is for programmable trigger levels only
(Table D). The hysteresis values for Tables A-C are the next higher and next lower trigger levels in Tables A-C
(See
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see
If using the Auto CTS interrupt:
F
2.14
2.15
2.16
OTE
IGURE
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
Enable auto CTS flow control using EFR bit-7.
: Table-B selected as Trigger Table for
Table
Receive Data
Byte and Errors
9. R
Auto RTS Hardware Flow Control
128 bytes by 11-bit
Auto RTS Hysteresis
Auto CTS Flow Control
11).
16X Clock
ECEIVER
wide
FIFO
O
PERATION IN
Figure
Receive Data Shift
Register (RSR)
Data FIFO
FIFO
10):
Receive
Receive
Data
Figure 9 (Table
AND
A
UTO
Validation
Data falls to
Data Bit
Data fills to
Trigger=16
RTS F
Example
FIFO
24
8
11).
16
: - RX FIFO trigger level selected at 16
LOW
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
(See Note Below)
Figure
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
C
ONTROL
bytes
10):
M
ODE
Receive Data Characters
Table 15
shows the complete
áç
áç
áç
áç
RXFIFO1
REV. 2.0.1