xr16c2850im Exar Corporation, xr16c2850im Datasheet - Page 25

• Manufacturer Part Number: xr16c2850im
• Description: Dual Uart With Tx And Rx Fifo Counters, 128 Bytes Of Fifos And Automatic Rs-485 Half Duplex Control
• Manufacturer: Exar Corporation

xr
REV. 2.1.3
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
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The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
associated with each of these interrupt levels.
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4.4
4.4.1
4.4.2
P
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
LOW to HIGH.
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control enabled
by EFR bit-7.
RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control enabled
by EFR bit-6.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
Special character interrupt is cleared by a read to ISR or after the next character is received.
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
RIORITY
L
EVEL
1
2
3
4
5
6
Interrupt Status Register (ISR) - Read-Only
Interrupt Generation:
Interrupt Clearing:
B
IT
0
0
0
0
0
0
Table
-5
B
9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
IT
0
0
0
0
0
1
-4
ISR R
B
EGISTER
IT
T
0
1
0
0
0
0
ABLE
-3
9: I
B
S
IT
TATUS
1
1
1
0
0
0
-2
NTERRUPT
B
B
ITS
IT
1
0
0
1
0
0
-1
S
OURCE AND
25
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
B
IT
0
0
0
0
0
0
-0
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
RXRDY (Received Xoff or Special character)
P
RIORITY
L
EVEL
S
OURCE OF INTERRUPT
XR16C2850