xr17l154iv Exar Corporation, xr17l154iv Datasheet - Page 22
xr17l154iv
Manufacturer Part Number
xr17l154iv
Description
3.3v Pci Bus Quad Uart
Manufacturer
Exar Corporation
Datasheet
1.XR17L154IV.pdf
(56 pages)
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Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (2
serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data
sampling. The BRG divisor (DLL and DLM registers) defaults to a random value upon power up. Therefore, the
BRG must be programmed during initialization to the operating data rate.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability for selecting the
operating data rate.
clock at 16X clock rate. At 8X sampling rate, these data rates would double. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated with the following equation(s).
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4.1
DISCONTINUED
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16),
divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8),
Programmable Baud Rate Generator
F
IGURE
XTAL1
XTAL2
Table 9
8. B
AUD
shows the standard data rates available with a 14.7456 MHz crystal or external
R
C rystal
ATE
Buffer
O sc/
G
C hannels
To O ther
ENERATOR
D ivide by 4
D ivide by 1
Prescaler
Prescaler
22
M C R Bit-7=0
M C R Bit-7=1
(default)
16
-1) to obtain a 16X or 8X sampling clock of the
D LL and D LM
Baud R ate
G enerator
R egisters
Logic
WITH
WITH
8XMODE [3:0]
8XMODE [3:0]
3.3V PCI BUS QUAD UART
R ate C lock to
and R eceiver
Transm itter
16X or 8X
Sam pling
IS
IS
1
0
XR17L154
REV. 1.1.0
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