pt7a4402b Pericom Technology Inc, pt7a4402b Datasheet - Page 7

• Manufacturer Part Number: pt7a4402b
• Description: T1/e1 System Synchronizer
• Manufacturer: Pericom Technology Inc

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Functional Description
Overall Operation
The PT7A4402B/4402L is a multitrunk synchronizer that pro-
vides the clock and frame signals for T1 and E1 primary rate
digital transmission links.
It basically consists of the Clock Generator, Mode/State Con-
trol Machine, Time Interval Error (TIE) Corrector, Digital Phase-
Locked Loop (DPLL), Input Impairment Monitor and Output
Interface Circuit.
The DPLL circuit provides synchronization of the output sig-
nals with any given input reference signal, and the TIE circuit
ensures phase continuity whenever the input reference signal
source is changed.
Referring to the block diagram on Page 3, the detailed functions
of the PT7A4402B/4402L are described as follows.
Master Clock
The PT7A4402B/4402L uses either an external clock source or
an external crystal and a few discrete components with its inter-
nal oscillator as the master clock.
Reference Select MUX
The PT7A4402B/4402L accepts two independent reference sig-
nals, the primary reference and secondary reference. Either one
of them is selected by the Reference Select MUX circuit and
sent to the TIE circuit. The selection is decided according to
the availability and quality of the reference signals, the mode
operation, and State. Refer to Tables 3, 6 and 7.
PT0100(12/05)
Figure 3. TIE Corrector
Select MUX
PRI or SEC
From
Frequency Select MUX
Feedback Signal
From
TCLR
Comparing
Circuit
TIE Corrector Enable
Mode/State Machine
Delay Value
From
7
Feedback Frequency Select MUX
The feedback frequency is selected by FS1 and FS2 (as shown
in Table 3) to match the particular incoming reference frequency
(1.544MHz, 2.048MHz or 8kHz). A reset (RST) must be performed
after every frequency select input change.
Time Interval Error (TIE) Corrector
The purpose of the TIE corrector is to allow the phase of the
output signals to be constant while switching between two
mutually incoherent reference signal input sources. Whenever
a new input reference signal is selected, the TIE corrector mea-
sures the phase difference between it and the feedback signal
and aligns them using a variable delay circuit. Thus, the TIE
Corrector output a virtual reference input signal for the DPLL
that has the same phase as it had for the previous reference
signal input source. Thus, the PT7A4402B/4402L provides a
totally seamless (glitch-free) transition from one reference sig-
nal to another. The TIE Corrector diagram is shown in Figure 3.
Table 3. Feedback Frequency Selection
F 2
F 2
F 2
F 2
F
S
S
S
S
S
0
0
1
1
2
Programmable
Circuit
Delay
T1/E1 System Synchronizer
F 1
F 1
F 1
F 1
F
S
S
S
0
0
S
S
1
1
1
PT7A4402B/4402L
n I
n I
n I
n I
n I
Virtual Reference
p
p
p
p
p
t u
t u
t u
t u
t u
1
2
R
To DPLL
0 .
5 .
Signal
e
k 8
Data Sheet
r F
r F
r F
r F
r F
8 4
4 4
e s
H
v r
q e
q e
q e
q e
q e
M
M
z
d e
H
H
u
u
u
u
u
n e
n e
n e
n e
n e
z
z
y c
y c
y c
y c
y c
Ver:1