ICS83940-02 Integrated Circuit System, ICS83940-02 Datasheet

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ICS83940-02

Manufacturer Part Number
ICS83940-02
Description
Manufacturer
Integrated Circuit System
Datasheet
LVCMOS_CLK
G
standard differential input levels. The single ended clock in-
put accepts LVCMOS or LVTTL input levels.The low imped-
ance LVCMOS outputs are designed to drive 50Ω series or
parallel terminated transmission lines. The effective fanout can
be increased from 18 to 36 by utilizing the ability of the out-
puts to drive two series terminated lines.
The ICS83940-02 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS83940 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
B
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83940AY-02
HiPerClockS™
,&6
LOCK
ENERAL
CLK_SEL
nCLK0
CLK0
D
The ICS83940-02 is a low skew, 1-to-18 Fanout
Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The 83940-02 has two selectable clock in-
puts. The CLK0, nCLK0 pair can accept most
IAGRAM
D
ESCRIPTION
0
1
www.icst.com/products/hiperclocks.html
PRELIMINARY
Q0
Q1 - Q16
Q17
1
D
P
LVCMOS_CLK
F
• 18 LVCMOS outputs, 7Ω typical output impedance
• Selectable LVCMOS clock or CLK0, nCLK0 input pair
• LVCMOS_CLK supports the following input types:
• CLK0, nCLK0 pair can accept the following differential input
• Maxmim output frequency up to 200MHz
• Output skew: 150ps (maximum)
• Part-to-part skew: TBDps (maximum)
• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Pin compatible with the MPC940L in single supply
IFFERENTIAL
IN
LVCMOS or LVTTL
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
applications
EATURES
CLK_SEL
A
GND
GND
nCLK
V
CLK
V
DDO
SSIGNMENT
DD
7mm x 7mm x 1.4mm package body
1
2
3
4
5
6
7
8
-
32 31 30 29 28 27 26 25
TO
9 10 11 12 13 14 15 16
ICS83940-02
-LVCMOS F
32-Lead LQFP
Y Pacakge
Top View
L
ICS83940-02
OW
REV. A SEPTEMBER 24, 2001
S
ANOUT
KEW
24
23
22
21
20
19
18
17
, 1-
Q6
Q7
Q8
V
Q9
Q10
Q11
GND
DDO
B
TO
UFFER
-18

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