xrt73r12 Exar Corporation, xrt73r12 Datasheet
xrt73r12
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xrt73r12 Summary of contents
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... OCTOBER 2007 GENERAL DESCRIPTION The XRT73R12 is a twelve channel fully integrated Line Interface Unit (LIU) featuring EXAR’s R Technology (Reconfigurable, Relayless Redundancy) for E3/DS3/STS-1 applications. The LIU incorporates 12 independent Receivers and Transmitters in a single 420 Lead TBGA package. Each channel of the XRT73R12 independently configured to operate in E3 (34 ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT FEATURES RECEIVER 3 R Technology (Reconfigurable, Redundancy) On chip Clock and Data Recovery circuit for high input jitter tolerance Meets E3/DS3/STS-1 Jitter Tolerance Requirement Detects and Clears LOS as per G.775 Receiver Monitor mode handles flat ...
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... C T LEARANCE HRESHOLDS FOR A GIVEN SETTING OF E3 ITU-T G.775 .................................................................................................. 23 AS PER E3 ITU-T G.775................................................................................................... 24 AS PER S DS3/STS-1 ...................................................................................................... FOR S E3. ................................................................................................................... FOR ................................................................................................................................. 25 ........................................................................................................ 25 ...................................................................................................................................... 27 XRT73R12 ( DUAL T ............................................................................................................................... 28 IMING ( NCODER AND ECODER ARE NABLED I XRT73R12 ............................................ 19 ICROPROCESSOR REQEN (DS3 STS-1 A AND - ) .............................................. 27 RAIL DATA ) ...
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... MICROPROCESSOR INTERFACE BLOCK ........................................................................................ ABLE ELECTING THE ICROPROCESSOR F 34 IGURE IMPLIFIED LOCK IAGRAM OF THE 7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 46 T 14: XRT73R12 M ABLE ICROPROCESSOR 7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION .......................................................................... 47 F 35. A µP I IGURE SYNCHRONOUS NTERFACE T 15 ABLE SYNCHRONOUS IMING PECIFICATIONS F 36 ...
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... T 37 ABLE ECEIVE ONTROL EGISTER T 38: XRT73R12 R MAP ABLE EGISTER SHOWING T 39 ABLE HANNEL ONTROL EGISTER T 40: XRT73R12 R MAP ABLE EGISTER SHOWING T 41 MSB R ABLE RROR OUNTER YTE EGISTER T 42: XRT73R12 R MAP ABLE EGISTER SHOWING T 43 LSB ...
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... Transmit Clock Input These input pins have three functions: • They function as the timing source for the Transmit Section of the corresponding channel within the XRT73R12. • They are used by the Transmit Section of the LIU IC to sample the corresponding TxPOS_n and TxNEG_n input pins. ...
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... Transmit TTIP Output - Positive Polarity Signal These output pins along with the corresponding TRING_n output pins, function as the Transmit DS3/E3/STS-1 Line output signal drivers for a given channel of the XRT73R12. Connect this signal and the corresponding TRING_n output signal to a 1:1 transformer. ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS IGNAL AME YPE C23 MTip0 AD23 MTip1 D19 MTip2 AC19 MTip3 D15 MTip4 AC15 MTip5 E11 MTip6 AB11 MTip7 E8 MTip8 AB8 MTip9 C4 MTip10 AD4 MTip11 ...
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... The data output via this pin is updated upon the active edge of RxCLK_n output clock signal. Single-Rail Mode - Receive Data Output In the Single-Rail Mode, all Receive (or Recovered) data will be output via this pin. The data output via this pin is updated upon the active edge of the RCLK_n output clock signal. 6 XRT73R12 ...
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... RxCLK11 D ESCRIPTION Receive Negative Data Output/Line Code Violation The function of these pins depends on whether the XRT73R12 is configured in Single Rail or Dual Rail mode. Dual-Rail Mode - Receive Negative Polarity Data Output In the Dual-Rail Mode, all negative-polarity data will be output via this pin. The positive-polarity data will be output via the corresponding RxPOS_n output pin ...
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... ESCRIPTION Receive TIP Input These input pins along with the corresponding RRing_n input pin function as the Receive DS3/E3/STS-1 Line input signal for a given channel of the XRT73R12. Cconnect this signal and the corresponding RRING_n input signal to a 1:1 transformer. Whenever the RTIP/RRING input pins are receiving a positive-polarity pulse within the incoming DS3 STS-1 line signal, this input pin will be pulsed to a higher voltage than its corresponding RRING_n input pin ...
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... CLKOUT11 D ESCRIPTION Single Frequency Mode Enable This input pin is used to configure the XRT73R12 to operate in the SFM (Single Frequency Mode). When this feature is invoked, the SFM Synthesizer will become active. By applying a 12.288MHz clock signal to the STS-1Clk/12M pin, the XRT73R12 will generate all of the appropriate clock signals (e.g., 34.368MHz, 44.736MHz or 51 ...
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... This pin controls the Microprocessor Parallel Interface mode. "High" sets a Synchronous clocked interface mode with a clock from the Host. "Low" sets an Asynchronous mode where a clock internal to the XRT73R12 will time the operations. High speed clock supplied by the Host to provide timing in the Synchronous Interface mode ...
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... This pin will remain "Low" until the Interrupt has been serviced. 2. This pin must be pulled "High" with a 3k RESET Input Pulsing this input "Low" causes the XRT73R12 to reset the contents of the on- chip Command Registers to their default values consequence, the XRT73R12 will then also be operating in its default condition. ...
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... DVDD should be isolated from the analog power supplies. For best results, use an internal power plane for isolation internal power plane is not available, a ferrite bead can be used. Every two DVDD power supply pins should be bypassed to ground through at least one 0.1 F capacitor. 12 XRT73R12 ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT GROUND PINS AME IN UMBERS RGND0 A22 RGND1 AF22 RGND2 A18 RGND3 AF18 RGND4 E14 RGND5 AB14 RGND6 E13 RGND7 AB13 RGND8 D9 RGND9 AC9 RGND10 A5 RGND11 AF5 TGND0 A23 TGND1 AF23 TGND2 A19 ...
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... D10 MRing6 RRing10 D11 DGND DVDD D12 DGND TTip8 D13 RTip6 AGND D14 DGND RRing8 D15 MTip4 AGND D16 DGND TTip6 D17 AGND 14 XRT73R12 ABLE IST UMBER AME IN IN AME D18 RVDD2 D19 MTip2 D20 ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT ABLE IST BY IN ABLE N UMBER AME IN E24 RxCLK0 H26 E25 RxPOS0 J1 E26 DGND J2 F1 DGND J3 F2 DVDD J4 F3 RxNEG/LCV8 J5 F4 RxNEG/LCV10 J22 F5 TxCLK10 J23 F22 TxCLK0 J24 F23 RxNEG/LCV0 ...
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... AD2 RLOS11 TMS AD3 TTip11 TxPOS1 AD4 MTip11 TxNEG1 AD5 RRing11 RLOL1 AD6 DVDD RxNEG/LCV11 AD7 TTip9 RxCLK11 AD8 AGND DGND AD9 RRing9 16 XRT73R12 ABLE IST UMBER AME IN IN AME AD10 AGND AD11 TTip7 AD12 ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT ABLE IST BY IN ABLE N UMBER AME IN AE16 TRing5 AF22 AE17 DGND AF23 AE18 RTip3 AF24 AE19 TVDD3 AF25 AE20 TRing3 AF26 AE21 DGND AE22 RTip1 AE23 TVDD1 AE24 TTip1 ...
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... REV. 1.0.3 FUNCTIONAL DESCRIPTION The XRT73R12 is a twelve channel fully integrated Line Interface Unit featuring EXAR’s R (Reconfigurable, Relayless Redundancy) for E3/DS3/STS-1 applications. independent Receivers and Transmitters in a single 420 Lead TBGA package. independently programmed to support E3, DS-3 or STS-1 line rates using one input clock reference of 12 ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 2.0 CLOCK SYNTHESIZER The LIU uses a flexible user interface for accepting clock references to generate the internal master clocks used to drive the LIU. The reference clock used to supply the microprocessor timing is generated from the DS SFM clock input. Therefore, if the chip is configured for STS-1 only or E3 only, then the DS-3 input pin must be connected to the STS-1 pin or E3 pin respectively. In DS-3 mode or when SFM is used, the STS-1 and E3 input pins can be left unconnected. If SFM is enabled by pulling the SFM_EN pin " ...
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... E3Clk input pin IGURE LOCK ISTRIBUTION ONGIFURED IN DS3Clk E3Clk N : For one input clock reference, the single frequency mode should be used. OTE TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT SFM ODE ITHOUT SING CLKOUT_n Clock Synthesizer LOL_n Processor 20 XRT73R12 ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 3.0 THE RECEIVER SECTION The receiver is designed so that the LIU can recover clock and data from an attenuated line signal caused by cable loss or flat loss according to industry specifications. Once data is recovered processed and presented at the receiver outputs according to the format chosen to interface with a Framer/Mapper or ASIC. ...
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... OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output pin is toggled “High” and the RLOS_n bit is set to “1” in the status control register. TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT D IAGRAM Peak Detector Slicer AGC/ Equalizer LOS Detector 22 XRT73R12 ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT ALOS (A LOS) D ABLE HE NALOG REQEN (DS3 A REQEN S PPLICATION ETTING DS3 0 1 STS 3.5.2 Disabling ALOS/DLOS Detection For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Writing a “1” to both ALOSDIS_n and DLOSDIS_n bits disables the LOS detection on a per channel basis. ...
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... DS3 DS3/STS-1 EST ET UP FOR Attenuator ∑ Cable Simulator T S E3. EST ET UP FOR Attenuator 1 Attenuator 2 ∑ Cable Simulator 24 XRT73R12 10 UI 255 G.775 Compliance DUT XRT73R12 Test Equipment DUT XRT73R12 Test Equipment ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT T ABLE M C ODE ABLE E3 DS3 STS-1 3.5.5 Muting the Recovered Data with LOS condition: When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the internal master clock outputs this clock onto the RxClk_n output pin. The data on the RxPOS_n and RxNEG_n pins can be forced to zero by setting the LOSMUT_n bits in the individual channel control register to “ ...
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... Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on the RLCV_n output pins to indicate line code violation. TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT MIN 45 34.368 44.736 51.84 26 XRT73R12 TYP MAX UNITS MHz MHz MHz ...
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... YPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE Terminal Equipment (E3/DS3 or STS-1 Framer) Figure 13. D IAGRAM Tx Timing Pulse Control Shaping Tx Control Figure 14. TxPOS TPData Transmit TxNEG TNData Logic Block TxLineClk TxClk Exar E3/DS3/STS-1 LIU 27 REV. 1.0.3 TxClk_n HDB3/ TxPOS_n B3ZS MUX Encoder TxNEG_n TxON Channel n XRT73R12 ( - ) DUAL RAIL DATA ...
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... TPData TxClk TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 15 RANSMITTER ERMINAL NPUT t FTX t t TSU THO ATA ORMAT NCODER AND ECODER ARE XRT73R12 T IMING MIN TYP MAX UNITS 34.368 MHz 44.736 MHz 51.84 MHz ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT F 17 IGURE UAL AIL ATA ORMAT Data 0 TPData TNData TxClk 4.2 Transmit Clock The Transmit Clock applied via TxClk_n pins, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736 MHz or STS-1 = 51.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 50% duty cycle clock to the pulse shaping circuit ...
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... DSX3 or STSX-1 is greater than 225 feet, disable the Transmit Build Out Circuit. TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT EST IRCUIT R1 TTIP(n) TPData(n) 31.6 +1% TNData(n) R2 TxClk(n) TRing(n) 31 XRT73R12 Figure 20 1:1 ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 4.5 E3 line side parameters The XRT73R12 line output at the transformer output meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure 21 ...
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... Signal Level to Clear Loss of Signal Occurence of LOS to LOS Declaration Time Termination of LOS to LOS Clearance Time N : The above values are OTE TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 0.90 0.95 12.5 R ECEIVER LINE SIDE INPUT CHARACTERISTICS 0. and V = 3.3 V± 5 XRT73R12 MIN TYP MAX UNITS 1.00 1. 1.00 1.05 14.55 16.5 ns 0.02 0. ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT F 22. B GR-253 CORE T IGURE ELLCORE 1.2 1 0.8 0.6 0.4 0 IME IN NIT NTERVALS < < -0.85 T -0.38 < < -0.38 T 0.36 < < 0.36 T 1.4 < < -0.85 T -0.68 < < -0.68 T 0.26 < < 0. RANSMIT UTPUT ULSE EMPLATE FOR ST S-1 Pulse T emplate Time STS ABLE ULSE ...
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... TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT IDE UTPUT AND ECEIVER INE 0.65 0.90 0.90 R ECEIVER LINE SIDE INPUT CHARACTERISTICS 0. and V = 3.3 V ± 5 DS3 B EMPLATE FOR AS PER ELLCORE DS3 Pulse T emplate Tim XRT73R12 (GR-253) IDE NPUT PECIFICATIONS NITS 0.75 0. 1.00 1. 8.6 9.65 10 ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT IME IN NIT NTERVALS < < -0.85 T -0.36 < < -0.36 T 0.36 < < 0.36 T 1.4 < < -0.85 T -0.68 < < -0.68 T 0.36 < < 0. DS3 T L ABLE RANSMITTER INE P ARAMETER T RANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude ...
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... This feature provides support for Redundancy the XRT73R12 is configured in Host mode, to permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writing a “1” to the TxON_n control bits transfers the control to TxON pin. ...
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... Bellcore GR-499 CORE specifies the minimum requirement of jitter tolerance for Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. as per GR-499 specification. Figure 25, jitter is introduced by the sinusoidal Data DUT XRT73R12 Clock Figure 26 37 REV. 1.0.3 Error Detector shows the jitter tolerance curve ...
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... E3/DS3/STS-1 compliant component must tolerate. versus the modulation frequency for various standards. TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT F DS3/STS 0 JITTER FREQUENCY (kHz) Table 10 38 XRT73R12 GR-253 STS-1 GR-499 Cat II GR-499 Cat I XRT73R12 20 100 ITU-T G.823 XRT73R12 800 below shows the jitter amplitude ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT T 10 ABLE ITTER MPLITUDE VERSUS I J NPUT ATE S TANDARD ( / ) 34368 ITU-T G.823 1.5 44736 GR-499 5 CORE Cat I 44736 GR-499 10 CORE Cat II 51840 GR-253 15 CORE Cat II 5 ITTER RANSFER Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency ...
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... The bandwidth is set according to the data rate. In general, the jitter is measured over a band of frequencies. TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT XRT73R12 ...
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... Any subsequent single bit error insertion must be done by first writing a “0” to INSPRBS bit and followed by a “1”. Figure 29 shows the status of RNEG/LCV pin when the XRT73R12 is configured in PRBS mode PRBS mode, the device is forced to operate in Single-Rail Mode. ...
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... REV. 1.0.3 6.2 LOOPBACKS The XRT73R12 offers three loopback modes for diagnostic purposes. The loopback modes are selected via the RLB_n and LLB_n bits n the Channel control registers select the loopback modes. 6.2.1 ANALOG LOOPBACK In this mode, the transmitter outputs TTIP_n and TRing_n are internally connected to the receiver inputs ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 6.2.2 DIGITAL LOOPBACK When the Digital Loopback is selected, the transmit clock TxClk_n and transmit data inputs (TxPOS_n & TxNEG_n are looped back and output onto the RxClk_n, RxPOS_n and RxNEG_n pins as shown in Figure 31 ...
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... TAOS does not operate in Analog loopback or Remote loopback modes, however will function in Digital loopback mode (TAOS) IGURE RANSMIT LL NES TxCLK HDB3/B3ZS TxPOS ENCODER TxNEG RxCLK HDB3/B3ZS RxPOS DECODER RxNEG TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT TIMING CONTROL TAOS DATA & CLOCK RECOVERY 44 XRT73R12 TTIP Tx Transmit All 1's TRing RTIP Rx RRing ...
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... MICROPROCESSOR INTERFACE BLOCK The Microprocessor Interface section supports communication between the local microprocessor (µP) and the LIU. The XRT73R12 supports a parallel interface asynchronously or synchronously timed to the LIU. The mi- croprocessor interface is selected by the state of the Pmode input pin. Selecting the microprocessor interface ...
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... Read/Write access Chip Select Input This active low signal selects the microprocessor interface of the XRT73R12 LIU and enables Read/Write operations with the on-chip register locations Read Signal This active low input functions as the read signal from the local pin is pulled “ ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 7 SYNCHRONOUS AND YNCHRONOUS Whether the LIU is configured for Asynchronous or Synchronous mode, the following descriptions apply. The synchronous mode requires an input clock (PCLK used as the microprocessor timing reference. Read and Write operations are described below. ...
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... D P IGNALS URING ROGRAMMED t 0 Valid Data for Readback YNCHRONOUS IMING PECIFICATIONS XRT73R12 NITS - I EAD AND RITE PERATIONS WRITE OPERATION Valid Address Data Available to Write Into the LIU ...
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... Source Level Interrupt Enable Register - Ch 1 ISR1 RUR Source Level Interrupt Status Register - Ch 1 AS1 R/O Alarm Status Register - Ch 1 TC0 R/W Transmit Control Register - Ch 1 RC1 R/W Receive Control Register - Ch 1 CC1 R/W Channel Control Register - Ch 1 EM1 R/W Error counter MSByte REV. 1.0.3 XRT73R12 R N EGISTER AME Reserved Reserved ...
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... IER3 R/W Source Level Interrupt Enable Register - Ch 3 ISR3 RUR Source Level Interrupt Status Register - Ch 3 AS3 R/O Alarm Status Register - Ch 3 TC3 R/W Transmit Control Register - Ch 3 RC3 R/W Receive Control Register - Ch 3 CC3 R/W Channel Control Register - XRT73R12 R N EGISTER AME Reserved Reserved ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT DDRESS OMMAND EGISTER ( ECIMAL 0x3A CR58 0x3B CR59 0x3C CR60 0x3D 0x3E 0x3F 0x40 0x41 CR65 0x42 CR66 0x43 CR67 0x44 CR68 0x45 CR69 0x46 CR70 0x47 CR71 0x48 0x49 0x4A CR74 ...
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... TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT L T ABEL YPE ) EM5 R/W Error counter MSByte Ch 5 EL5 R/W Error counter LSbyte EH5 R/W Error counter Holding register CIE R/W Channel 0-5 Interrupt Enable flags CIS R/O Channel 0-5 Interrupt status flags PN R/O Device Part Number Register VN R/O Chip Revision Number Register 52 XRT73R12 R N EGISTER AME ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT DDRESS OMMAND EGISTER ( ECIMAL 0x75 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 CR128 0x81 CR129 0x82 CR130 0x83 CR131 0x84 CR132 0x85 CR133 0x86 CR134 0x87 CR135 0x88 CR136 0x89 0x8A ...
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... HANNEL ONTROL EGISTERS IER9 R/W Source Level Interrupt Enable Register - Ch 9 ISR9 RUR Source Level Interrupt Status Register - Ch 9 AS9 R/O Alarm Status Register - Ch 9 TC9 R/W Transmit Control Register - Ch 9 RC9 R/W Receive Control Register - XRT73R12 R N EGISTER AME Reserved Reserved ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT DDRESS OMMAND EGISTER ( ECIMAL 0xB6 CR182 0xB7 CR183 0xB8 0xB9 0xBA CR186 0xBB CR187 0xBC CR188 0xBD 0xBE 0xBF 0xC0 0xC1 CR193 0xC2 CR194 0xC3 CR195 0xC4 CR196 0xC5 CR197 0xC6 CR198 ...
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... ABEL YPE ) RC11 R/W Receive Control Register - Ch 11 CC11 R/W Channel Control Register - Ch 11 EM11 R/W Error counter MSByte Ch 11 EL11 R/W Error counter LSbyte EH11 R/W Error counter Holding register CIE R/W Channel 6-11 Interrupt enable flags CIS R/O Channel 6-11 Interrupt status flags 56 XRT73R12 R N EGISTER AME Reserved ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT DDRESS OMMAND EGISTER ( ECIMAL 0xF5 0xF6 0xF7 0xF8 0xF5 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF L T ABEL YPE ) 57 REV. 1.0 EGISTER AME ...
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... REV. 1.0.3 THE GLOBAL/CHIP-LEVEL REGISTERS The register set, within the XRT73R12 contains ten global or chip-level registers. These registers control operations in more than one channel or apply to the complete chip. This section will present detailed information on the Global Registers. T 18: L ABLE C OMMAND A DDRESS R EGISTER ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT T 20: APS/R ABLE EDUNDANCY Reserved Reserved RxON AME YPE N UMBER 7,6 Reserved 5 RxON Ch 5 R/W Receive Section ON - Channel n 4 RxON Ch 4 This READ/WRITE bit-field is used to turn on or turn off the Receiver associated with Channel per channel basis ...
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... RRING_ n input pins in a high impedance state Turns on the Receive Driver associated with Channel n. TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT CR136 (A ECEIVE ONTROL EGISTER RxON Ch 10 RxON Ch 9 RxON Ch 8 R/W R/W D ESCRIPTION 60 XRT73R12 88) DDRESS OCATION RxON Ch 7 RxON Ch 6 R/W R/W R/W ...
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... To enable Channel n for Interrupt Generation at the Channel Level • To disable all Interrupts associated with Channel n within the XRT73R12 This is a "master" enable bit for each channel. This bit allows control on a per channel basis to signal the Host of selected error conditions bit is cleared, no interrupts from that channel will be sent to the Host via the INT ...
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... Interrupt Enable register (IERn) for the channel will activate the INT pin to the Host Disables all Channel n related Interrupts Enables Channel n-related Interrupts. The user must enable individual Channel n related Interrupts at the source level, before they are can generate an interrupt. 62 XRT73R12 DDRESS OCATION X ...
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... D YPE R/O Channel n Interrupt Status Bit: This READ-ONLY bit-field indicates whether the XRT73R12 has a pending Channel n-related interrupt that is awaiting service. The first six channels are serviced through this location and the other six at address 0xE1. These two registers are used by the Host to identify the source channel of an active interrupt ...
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... YPE R/O Channel n Interrupt Status Bit: This READ-ONLY bit-field indicates whether the XRT73R12 has a pending Channel n-related interrupt that is awaiting service. The last six channels are serviced through this location and the other six at address 0x61. These two registers are used by the Host to identify the source channel of an active interrupt ...
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... Chip Revision Number Value: This READ-ONLY register contains a value that represents the current revision of this XRT73R12. This revision num- ber will always be in the form of "0x0#", where "#" hexa- decimal value that specifies the current revision of the chip. ...
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... REV. 1.0.3 THE PER-CHANNEL REGISTERS The XRT73R12 consists of 120 per-Channel Registers (12 channels and 10 registers per channel). Table 9 presents the overall Register Map with the Per-Channel Registers unshaded. REGISTER DESCRIPTION - PER CHANNEL REGISTERS T 28: XRT73R12 R ABLE EGISTER A DDRESS OCATION 0x0- APST ...
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... Enable - Ch 0: This READ/WRITE bit-field is used to enable or disable the Change of the Receive LOS Defect Condition Interrupt. If the user enables this interrupt, then the XRT73R12 will generate an interrupt any time any of the following events occur. • Whenever the Receive Section (within Channel n) declares the LOS Defect Condition. • ...
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... REV. 1.0.3 T 30: XRT73R12 R ABLE Reserved T 31 ABLE OURCE EVEL NTERRUPT UMBER AME Reserved 3 Change of FL Con- dition Interrupt Sta- tus 2 Change of LOL Con- RUR dition Interrupt Sta- tus TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT T 31 ABLE OURCE EVEL NTERRUPT UMBER AME 1 Change of LOS RUR Condition Interrupt Status 0 Change of DMO RUR Condition Interrupt Status TATUS EGISTER HANNEL [0:11] & = 0-5 & 8- YPE Change of Receive LOS (Loss of Signal) Defect Condition Interrupt ...
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... REV. 1.0.3 T 32: XRT73R12 R ABLE Reserved Loss of PRBS Digital LOS Pattern Sync Defect Declared R/O R ABLE LARM UMBER AME 7 Reserved 6 Loss of PRBS Pat- tern Lock TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT MAP A S EGISTER SHOWING ...
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... Defect condition OTES 1. LOS Detection (within each channel of the XRT73R12) is performed by both an Analog LOS Detector and a Digital LOS Detector. The LOS state of a given Channel is simply a WIRED the LOS Defect Declare states of these two detectors. 2. The current LOS Defect Condition (for the channel) can be determined by reading out the contents of Bit 1 (Receive LOS Defect Declared) within this register ...
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... The Transmit Section will clear the Transmit DMO Alarm condition upon detecting bipolar activity on the Transmit Output Line signal Indicates that the Transmit Section of Channel_n is NOT currently declar- ing the Transmit DMO Alarm condition Indicates that the Transmit Section of Channel_n is currently declaring the Transmit DMO Alarm condition. 72 XRT73R12 OCATION XM ESCRIPTION ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT T 34: XRT73R12 R ABLE EGISTER Reserved Internal Transmit Drive Monitor R/W T 35: T ABLE RANSMIT UMBER AME Reserved 5 Internal Transmit R/W Drive Monitor Enable 4 Insert PRBS Error R/W 3 Reserved MAP T C SHOWING ...
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... Section (of Channel_n) will always generate a DS3 pulse that complies with the Isolated Pulse Template requirements per Bellcore GR-499-CORE STS-1 pulse that complies with the Pulse Template requirements per Tel- cordia GR-253-CORE This bit-field is ignored if the channel has been configured to operate OTE in the E3 Mode. 74 XRT73R12 OCATION XM ESCRIPTION ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT T 36: XRT73R12 R ABLE Reserved Disable DLOS Detector R ABLE ECEIVE UMBER AME Reserved 5 Disable DLOS R/W Detector 4 Disable ALOS R/W Detector 3 RxCLKINV R/W MAP R C EGISTER SHOWING ECEIVE ONTROL ...
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... Disables the Receive Equalizer within the corresponding channel Enables the Receive Equalizer within the corresponding channel For virtually all applications, we recommend that the user set this bit- OTE field to "1" (for all channels) and enable the Receive Equalizer. 76 XRT73R12 OCATION XM ESCRIPTION ...
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... YPE PRBS Generator and Receiver Enable - Channel_n: This READ/WRITE bit-field is used to enable or disable the PRBS Generator and Receiver within a given Channel of the XRT73R12. If the user enables the PRBS Generator and Receiver, then the following will happen. 1. The PRBS Generator (which resides within the Transmit Section of ...
Page 81
... This READ/WRITE bit-field, along with Bit 1 (STS-1/DS3_n) within this reg- ister, is used to configure a given channel into either the DS3 STS-1 Modes Configures Channel_n to operate in either the DS3 or STS-1 Modes, depending upon the state of Bit 1 (STS-1/DS3_n) within this same register. 1- Configures Channel_n to operate in the E3 Mode. 78 XRT73R12 OCATION XM ESCRIPTION ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT T 39: C ABLE HANNEL UMBER AME 1 DS3 R/W STS- SR/DR_n R ONTROL EGISTER HANNEL N DDRESS ( = [0:11] & = 0-5 & 8- YPE STS-1/DS3 Mode Select - Channel_n: This READ/WRITE bit-field, along with Bit 2 (E3_n) is used to configure a given channel into either the DS3 STS-1 Modes. This bit-field is ignored if Bit 2 (E3_n) has been set to " ...
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... REV. 1.0.3 T 40: XRT73R12 R ABLE EGISTER A DDRESS OCATION 0x0- APST IER0 ISR0 AS0 0 1- IER1 ISR1 AS1 X 0x2- IER2 ISR2 AS2 0x3- IER3 ISR3 AS3 0x4- IER4 ISR4 AS4 0x5- IER5 ISR5 AS5 0x6- CIS CIE 0x7- 0x8- APST IER6 ...
Page 84
... IER11 ISR11 AS11 0xE- CIS CIE 0xF LSB ABLE RROR OUNTER 8th bit R/W R/W R/W T 44: XRT73R12 R ABLE EGISTER A DDRESS OCATION 0x0- APST IER0 ISR0 AS0 0 1- IER1 ISR1 AS1 X 0x2- IER2 ISR2 AS2 0x3- ...
Page 85
... REV. 1.0.3 T 44: XRT73R12 R ABLE EGISTER A DDRESS OCATION 0xE- CIE CIS 0xF ABLE RROR OUNTER OLDING Msb R/W R/W R/W Each channel contains a dedicated 16 bit PRBS error counter. When enabled this counter will accumulate PRBS errors (as well as excess zeros and LCVs). The LS byte will "carry" a one over to the MS byte each time it rolls over from 255 to zero until the MS byte also reaches 255. When both counters reach 255, no further errors will be accumulated and " ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 8.0 ELECTRICAL CHARACTERISTICS P SYMBOL ARAMETER V Supply Voltage DD V Input Voltage at any Pin IN I Input current at any pin IN S Storage Temperature TEMP A Ambient Operating Temperature TEMP Theta JA Thermal Resistance: Junction-to-Ambient Theta JC Thermal Resistance: Junction-to-Case ...
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... P CC Consumption DD Dissipation TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 47 LECTRICAL HARACTERISTICS P ARAMETER 23 -1 pattern 23 -1 pattern 23 -1 pattern 4mA = Delivered to Load 84 XRT73R12 : . . . MIN TYP MAX UNITS 3.135 3.3 3.465 V 3.135 3.3 3.465 V 1016 1117 mA 1040 1140 mA 1100 1210 mA 3 ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT P N ART UMBER XRT73R12IB PACKAGE DIMENSIONS - ORDERING INFORMATION P ACKAGE 420 TBGA 420 Tape Ball Grid Array ( mm, TBGA) Rev. 1. (A1 corner feature is mfger option) ...
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... XRT73R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT REVISION HISTORY R D EVISION ATE 1.0.0 April 2006 Final Release Version of XRT73R12 datasheet. 1.0.1 12/07/06 1.Corrrected package thermal resistance specification. 1.0.2 6/27/07 1. Corrected global register 0x08 and added global registers 0x80 & 0x88. 2. Added ( N 1.0.3 10/26/07 1. Theta-jC thermal value added. ...